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HCPL-2430-300 Datasheet(PDF) 10 Page - AVAGO TECHNOLOGIES LIMITED

Part # HCPL-2430-300
Description  20 MBd High CMR Logic Gate Optocouplers
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Manufacturer  AVAGO [AVAGO TECHNOLOGIES LIMITED]
Direct Link  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

HCPL-2430-300 Datasheet(HTML) 10 Page - AVAGO TECHNOLOGIES LIMITED

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10
Package Characteristics
Parameter
Sym.
Device
Min.
Typ.*
Max. Units Test Conditions
Fig.
Note
Input-Output
V
ISO
3750
V rms
RH ≤50%,
3, 13
Momentary
t = 1 min.,
Withstand Voltage**
T
A = 25°C
Input-Output
R
I-O
1012
Ω
V
I-O = 500 Vdc
3
Resistance
Input-Output
C
I-O
0.6
pF
f = 1 MHz
Capacitance
V
I-O = 0 Vdc
Input-Input
I
I-I
2430
0.005
µA
RH ≤45%
8
Insulation Leakage
t = 5 s,
Current
V
I-I = 500 Vdc
Resistance
R
I-I
2430
1011
Ω
V
I-I = 500 Vdc
8
(Input-Input)
Capacitance
C
I-I
2430
0.25
pF
f = 1 MHz
8
(Input-Input)
*All typical values are at T
A = 25°C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if applicable), your equipment lev-
el safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number 5963-2203E.
Notes:
1. Each channel.
2. Duration of output short circuit time not to exceed 10 ms.
3. Device considered a two terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
4. t
PHL propagation delay is measured from the 50% level on the rising edge of the input current pulse to the 1.5 V level on the falling edge of the
output pulse. The t
PLH propagation delay is measured from the 50% level on the falling edge of the input current pulse to the 1.5 V level on the
rising edge of the output pulse.
5. The typical data shown is indicative of what can be expected using the application circuit in Figure 13.
6. This specification simulates the worst case operating conditions of the HCPL-2400 over the recommended operating temperature and V
CC range
with the suggested application circuit of Figure 13.
7. Propagation delay skew is discussed later in this data sheet.
8. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
9. Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dV
CM/dt of the common mode pulse, VCM, to assure
that the output will remain in a Logic High state (i.e., V
O > 2.0 V). Common mode transient immunity in a Logic Low level is the maximum toler-
able (negative) dV
CM/dt of the common mode pulse, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V).
10. Power Supply Noise Immunity is the peak to peak amplitude of the ac ripple voltage on the V
CC line that the device will withstand and still remain
in the desired logic state. For desired logic high state, V
OH(MIN) > 2.0 V, and for desired logic low state, VOL(MAX) < 0.8 V.
11. Use of a 0.1 µF bypass capacitor connected between pins 8 and 5 adjacent to the device is required.
12. Peak Forward Input Current pulse width < 50 µs at 1 KHz maximum repetition rate.
13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500V rms for one second (leakage detec-
tion current limit, I
I-O ≤ 5 µA). This test is performed before the 100% Production test shown in the IEC/EN/DIN EN 60747-5-2 Insulation Related
Characteristics Table, if applicable.


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