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AM79761YC-14 Datasheet(PDF) 9 Page - Advanced Micro Devices |
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AM79761YC-14 Datasheet(HTML) 9 Page - Advanced Micro Devices |
9 / 20 page Am79761 9 PRELIMINARY FUNCTIONAL DESCRIPTION Overview The GigaPHY-SD device provides the PMA functionality for 1000BASE-X systems. The GigiaPHY-SD communi- cates with the PCS through the 10-bit code groups and communicates with the Physical Medium Dependent (PMD) layer to transmit and receive data from the net- work, through either fiber optic or copper coax media. The GigaPHY-SD device consists of the following functional blocks: n 1000BASE-X Transmit block including: — Clock Synthesizer — Serializer and Transmission interface n 1000BASE-X Receive block including: — Clock Recovery — Deserializer — Word Alignment and synchronization Clock Synthesizer The Am79761 clock synthesizer multiplies the refer- ence frequency provided on the REFCLK pin by 10 to achieve a baud rate clock at nominally 1.25 GHz. The clock synthesizer contains a fully monolithic PLL which does not require any external components. Serializer The Am79761 device accepts TTL input data as a par- allel 10-bit character on the TXD[0:9] bus which is latched into the input latch on the rising edge of REFCLK. This data will be serialized and transmitted on the TX PECL differential outputs at a baud rate of ten times the frequency of the REFCLK input, with bit TXD0 transmitted first. User data should be encoded for transmission using the 8B/10B block code de- scribed in the IEEE 802.3 specification. Transmission Character Interface An encoded byte is 10 bits and is referred to as a trans- mission character. The 10-bit interface on the Am79761 device corresponds to a transmission char- acter. This mapping is shown in Table 20. Table 20. Transmission Order and Mapping of an 8B/10B Character Clock Recovery The Am79761 device accepts differential high speed serial inputs on the RX ± pins, extracts the clock and retimes the data. The Am79761 clock recovery circuitry is completely monolithic and requires no external com- ponents. For proper operation, the baud rate of the data stream to be recovered should be within 0.01% of ten times the REFCLK frequency. For example, if the REFCLK used is 125 MHz, then the incoming serial baud rate must be 1.25 gigabaud ±0.01 percent. Deserializer The re-timed serial bit stream is converted into a 10-bit parallel output character. The Am79761 device provides complementary TTL recovered clocks, RCLK and RCLKN, which are at 1/20th of the serial baud rate. This architecture is designed to simplify demultiplexing of the 10-bit data characters into a 20-bit half-word in the downstream controller chip. The clocks are generated by dividing down the high-speed clock which is phase locked to the serial data. The serial data is re-timed by the internal high-speed clock and deserialized. The resulting parallel data will be captured by the adjoining protocol logic on the rising edges of RCLK and RCLKN. In order to maximize the setup and hold times available at this interface, the parallel data is loaded into the output register at a point nominally midway between the transition edges of RCLK and RCLKN. If serial input data is not present or does not meet the required baud rate, the Am79761 will continue to pro- duce a recovered clock so that downstream logic may continue to function. The RCLK and RCLKN output frequency under these circumstances may differ from their expected frequency by no more than ±1 percent. Parallel Data Bits T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 8B/10B Bit Position j h g f i e d c b a Comma Character X X X 1111100 Last Data Bit Transmitted First Data Bit Transmitted |
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