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VND5E012MY-E Datasheet(PDF) 23 Page - STMicroelectronics |
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VND5E012MY-E Datasheet(HTML) 23 Page - STMicroelectronics |
23 / 36 page ![]() DocID16503 Rev 5 23/36 VND5E012MY-E Application information 35 3 Application information Figure 29. Application schematic Note: Channel 2 has the same internal circuit as channel 1. 3.1 Load dump protection Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCCPK max rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table. 3.2 MCU I/Os protection When negative transients are present on the VCC line, the control pin is pulled negative to approximately -1.5 V. ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/Os pins from latching-up. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation 1 Calculation example: For VCCpeak = - 1.5 V; Ilatchup ≥ 20 mA; VOHμC ≥ 4.5 V 75 Ω ≤ Rprot ≤ 240 kΩ. v ccpeak llatchup ⁄ R prot V OH μC V IH – () ≤ l IHmax ⁄ ≤ |
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