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LTC1290DISW Datasheet(PDF) 4 Page - Linear Integrated Systems |
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LTC1290DISW Datasheet(HTML) 4 Page - Linear Integrated Systems |
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4 / 32 page  4 LTC1290 1290fe AC CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) LTC1290B/LTC1290C/LTC1290D SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSCLK Shift Clock Frequency VCC = 5V (Note 6) 0 2.0 MHz fACLK A/D Clock Frequency VCC = 5V (Note 6) (Note 10) 4.0 MHz tACC Delay Time from CS ↓ to DOUT Data Valid (Note 9) 2 ACLK Cycles tSMPL Analog Input Sample Time See Operating Sequence 7 SCLK Cycles tCONV Conversion Time See Operating Sequence 52 ACLK Cycles tCYC Total Cycle Time See Operating Sequence (Note 6) 12 SCLK + Cycles 56 ACLK tdDO Delay Time, SCLK ↓ to DOUT Data Valid See Test Circuits LTC1290BC, LTC1290CC ● 130 220 ns LTC1290DC, LTC1290BI LTC1290CI, LTC1290DI LTC1290BM, LTC1290CM ● 180 270 ns LTC1290DM (OBSOLETE) tdis Delay Time, CS ↑ to DOUT Hi-Z See Test Circuits ● 70 100 ns ten Delay Time, 2nd ACLK ↓ to DOUT Enabled See Test Circuits ● 130 200 ns thCS Hold Time, CS After Last SCLK ↓ VCC = 5V (Note 6) 0 ns thDI Hold Time, DIN After SCLK ↑ VCC = 5V (Note 6) 50 ns thDO Time Output Data Remains Valid After SCLK ↓ 50 ns tf DOUT Fall Time See Test Circuits ● 65 130 ns tr DOUT Rise Time See Test Circuits ● 25 50 ns tsuDI Setup Time, DIN Stable Before SCLK ↑ VCC = 5V (Note 6) 50 ns tsuCS Setup Time, CS ↓ Before Clocking in (Notes 6, 9) 2 ACLK Cycles First Address Bit + 100ns tWHCS CS High Time During Conversion VCC = 5V (Note 6) 52 ACLK Cycles CIN Input Capacitance Analog Inputs On Channel 100 pF Analog Inputs Off Channel 5 pF Digital Inputs 5 pF |
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