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ADS5287IRGCRG4 Datasheet(PDF) 11 Page - Texas Instruments

Part # ADS5287IRGCRG4
Description  10-Bit, Octal-Channel ADC Up to 65MSPS
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS5287IRGCRG4 Datasheet(HTML) 11 Page - Texas Instruments

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ADS5287
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SBAS428D – JANUARY 2008 – REVISED JUNE 2012
LVDS OUTPUT TIMING CHARACTERISTICS
(1)
Typical values are at +25°C, minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX =
+85°C, sampling frequency = as specified, CLOAD = 5pF
(2), I
OUT = 3.5mA, RLOAD = 100Ω
(3), and no internal termination, unless otherwise
noted.
ADS5287
40MSPS
50MSPS
65MSPS
PARAMETER
TEST CONDITIONS
(4)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Data valid
(6) to zero-crossing of
tSU
Data setup time
(5)
0.67
0.47
0.27
ns
LCLKP
Zero-crossing of LCLKP to data
tH
Data hold time
(5)
0.85
0.65
0.4
ns
becoming invalid
(6)
Input clock (ADCLK) rising edge
tPROP
Clock propagation delay
cross-over to output clock (ADCLKP)
10
14
16.6
10
12.5
14.1
9.7
11.5
14
ns
rising edge cross-over
Duty cycle of differential clock,
LVDS bit clock duty cycle
45.5
50
53
45
50
53.5
41
50
57
(LCLKP – LCLKN)
Bit clock cycle-to-cycle
250
250
250
ps, pp
jitter
Frame clock cycle-to-cycle
150
150
150
ps, pp
jitter
tRISE,
Data rise time, data fall
Rise time is from –100mV to +100mV
0.09
0.2
0.4
0.09
0.2
0.4
0.09
0.2
0.4
ns
tFALL
time
Fall time is from +100mV to –100mV
tCLKRISE,
Output clock rise time,
Rise time is from –100mV to +100mV
0.09
0.2
0.4
0.09
0.2
0.4
0.09
0.2
0.4
ns
tCLKFALL
output clock fall time
Fall time is from +100mV to –100mV
(1)
Timing parameters are ensured by design and characterization; not production tested.
(2)
CLOAD is the effective external single-ended load capacitance between each output pin and ground.
(3)
IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.
(4)
Measurements are done with a transmission line of 100
Ω characteristic impedance between the device and the load.
(5)
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as
reduced timing margin.
(6)
Data valid refers to a logic high of +100mV and a logic low of –100mV.
LVDS OUTPUT TIMING CHARACTERISTICS
(1)
Typical values are at +25°C, minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX =
+85°C, sampling frequency = as specified, CLOAD = 5pF
(2), I
OUT = 3.5mA, RLOAD = 100Ω
(3), and no internal termination, unless otherwise
noted.
ADS5287
30MSPS
20MSPS
10MSPS
PARAMETER
TEST CONDITIONS
(4)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Data valid
(6) to zero-crossing of
tSU
Data setup time
(5)
0.8
1.5
3.7
ns
LCLKP
Zero-crossing of LCLKP to data
tH
Data hold time
(5)
1.2
1.9
3.9
ns
becoming invalid
(6)
Input clock (ADCLK) rising edge
tPROP
Clock propagation delay
cross-over to output clock (ADCLKP)
9.5
13.5
17.3
9.5
14.5
17.3
10
14.7
17.1
ns
rising edge cross-over
Duty cycle of differential clock,
LVDS bit clock duty cycle
46.5
50
52
48
50
51
49
50
51
(LCLKP – LCLKN)
Bit clock cycle-to-cycle
250
250
750
ps, pp
jitter
Frame clock cycle-to-cycle
150
150
500
ps, pp
jitter
tRISE,
Data rise time, data fall
Rise time is from –100mV to +100mV
0.09
0.2
0.4
0.09
0.2
0.4
0.09
0.2
0.4
ns
tFALL
time
Fall time is from +100mV to –100mV
tCLKRISE,
Output clock rise time,
Rise time is from –100mV to +100mV
0.09
0.2
0.4
0.09
0.2
0.4
0.09
0.2
0.4
ns
tCLKFALL
output clock fall time
Fall time is from +100mV to –100mV
(1)
Timing parameters are ensured by design and characterization; not production tested.
(2)
CLOAD is the effective external single-ended load capacitance between each output pin and ground.
(3)
IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.
(4)
Measurements are done with a transmission line of 100
Ω characteristic impedance between the device and the load.
(5)
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as
reduced timing margin.
(6)
Data valid refers to a logic high of +100mV and a logic low of –100mV.
Copyright © 2008–2012, Texas Instruments Incorporated
11


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