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ADS7223SRHBT Datasheet(PDF) 11 Page - Texas Instruments

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Part # ADS7223SRHBT
Description  Dual, 1MSPS, 16-/14-/12-Bit, 4 2 or 2 2 Channel, Simultaneous Sampling Analog-to-Digital Converter
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS7223SRHBT Datasheet(HTML) 11 Page - Texas Instruments

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ADS8363
ADS7263
ADS7223
www.ti.com
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
TIMING CHARACTERISTICS
(1)
Over the recommended operating free-air temperature range of –40°C to +125°C, and DVDD = 2.3V to 5.5V, unless
otherwise noted.
ADS8363, 7263, 7223
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tDATA
Data throughput
fCLK = max
1
ms
Half-clock mode
17.5
tCLK
tCONV
Conversion time
Full-clock mode
35
tCLK
tACQ
Acquisition time
100
ns
Half-clock mode
0.5
20
MHz
fCLK
CLOCK frequency
Full-clock mode
1
40
MHz
Half-clock mode
50
2000
ns
tCLK
CLOCK period
Full-clock mode
25
1000
ns
tCLKL
CLOCK low time
11.25
ns
tCLKH
CLOCK high time
11.25
ns
t1
CONVST rising edge to first CLOCK rising edge
12
ns
10
ns
t2
CONVST high time
Half-clock mode: timing
1
tCLK
modes II and IV only
Half-clock mode: timing
t3
RD high time
modes II, IV, SII, and SIV
1
tCLK
only
tS1
RD high to CLOCK falling edge setup time
5
ns
tH1
RD high to CLOCK falling edge hold time
5
ns
tS2
Input data to CLOCK falling edge setup time
5
ns
tH2
Input data to CLOCK falling edge hold time
4
ns
2.3V < DVDD < 3.6V
19
ns
tD1
CONVST rising edge to BUSY high delay(2)
4.5V < DVDD < 5.5V
16
ns
CLOCK 18th falling edge (half-clock mode) or
2.3V < DVDD < 3.6V
25
ns
tD2
24th rising edge (full-clock mode) to BUSY low
4.5V < DVDD < 5.5V
20
ns
delay
Half-clock mode, 2.3V <
14
ns
DVDD < 3.6V
tD3
CLOCK rising edge to next data valid delay
Half-clock mode, 4.5V <
12
ns
DVDD < 5.5V
tH3
Output data to CLOCK rising edge hold time
Half-clock mode
3
ns
tD4
CLOCK falling edge to next data valid delay
Full-clock mode
19
ns
tH4
Output data to CLOCK falling edge hold time
Full-clock mode
7
ns
2.3V < DVDD < 3.6V
16
ns
tD5
RD falling edge to first data valid
4.5V < DVDD < 5.5V
12
ns
tD6
CS rising edge to SDOx 3-state
6
ns
(1)
All input signals are specified with tR = tF = 1.5ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2.
(2)
Not applicable in auto-sleep power-down mode.
Copyright © 2010–2011, Texas Instruments Incorporated
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Product Folder Link(s): ADS8363 ADS7263 ADS7223


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