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TAS5508PAGR Datasheet(PDF) 4 Page - Texas Instruments |
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TAS5508PAGR Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 105 page  TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 www.ti.com 6 Serial-Control I2C Register Summary .................................................................................... 69 7 Serial-Control Interface Register Definitions .......................................................................... 73 7.1 Clock Control Register (0x00) ............................................................................................ 73 7.2 General Status Register 0 (0x01) ........................................................................................ 73 7.3 Error Status Register (0x02) .............................................................................................. 74 7.4 System Control Register 1 (0x03) ........................................................................................ 74 7.5 System Control Register 2 (0x04) ........................................................................................ 74 7.6 Channel Configuration Control Registers (0x05–0x0C) ............................................................... 74 7.7 Headphone Configuration Control Register (0x0D) .................................................................... 75 7.8 Serial Data Interface Control Register (0x0E) .......................................................................... 75 7.9 Soft Mute Register (0x0F) ................................................................................................. 76 7.10 Automute Control Register (0x14) ....................................................................................... 77 7.11 Automute PWM Threshold and Back-End Reset Period Register (0x15) .......................................... 78 7.12 Modulation Index Limit Register (0x16) ................................................................................. 79 7.13 Interchannel Delay Registers (0x1B–0x22) ............................................................................. 79 7.14 Channel Offset Register (0x23) .......................................................................................... 79 7.15 Bank-Switching Command Register (0x40) ............................................................................. 79 7.16 Input Mixer Registers, Channels 1–8 (0x41–0x48) .................................................................... 80 7.17 Bass Management Registers (0x49–0x50) ............................................................................. 84 7.18 Biquad Filter Register (0x51–0x88) ...................................................................................... 84 7.19 Bass and Treble Bypass Register, Channels 1–8 (0x89–0x90) ..................................................... 85 7.20 Loudness Registers (0x91–0x95) ........................................................................................ 85 7.21 DRC1 Control Registers, Channels 1–7 (0x96) ........................................................................ 85 7.22 DRC2 Control Register, Channel 8 (0x97) .............................................................................. 87 7.23 DRC1 Data Registers (0x98–0x9C) ..................................................................................... 87 7.24 DRC2 Data Registers (0x9D–0xA1) ..................................................................................... 87 7.25 DRC Bypass Registers (0xA2–0xA9) .................................................................................... 88 7.26 8 ＝2 Output Mixer Registers (0xAA–0xAF) ............................................................................. 88 7.27 8 ＝3 Output Mixer Registers (0xB0–0xB1) ............................................................................. 89 7.28 Volume Biquad Register (0xCF) .......................................................................................... 91 7.29 Volume, Treble, and Bass Slew Rates Register (0xD0) .............................................................. 92 7.30 Volume Registers (0xD1–0xD9) .......................................................................................... 92 7.31 Bass Filter Set Register (0xDA) .......................................................................................... 94 7.32 Bass Filter Index Register (0xDB) ....................................................................................... 95 7.33 Treble Filter Set Register (0xDC) ........................................................................................ 95 7.34 Treble Filter Index (0xDD) ................................................................................................. 97 7.35 AM Mode Register (0xDE) ................................................................................................ 97 7.36 PSVC Range Register (0xDF) ............................................................................................ 99 7.37 General Control Register (0xE0) ......................................................................................... 99 7.38 Incremental Multiple-Write Append Register (0xFE) ................................................................... 99 8 TAS5508 Example Application Schematic ............................................................................ 101 Contents 4 Submit Documentation Feedback |
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