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TAS5719PHP Datasheet(PDF) 5 Page - Texas Instruments |
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TAS5719PHP Datasheet(HTML) 5 Page - Texas Instruments |
5 / 68 page CPN CPP PLL_FLTP VR_ANA HPVDD AVSS PLL_FLTM HPR_IN HPVSS HPL_OUT HPL_IN RESET HPR_OUT STEST DVDD DVSS GND VREG GVDD_OUT HP_SD BST_D AGND PVDD_CD SSTIMER P0075-11 PHP Package (TopView) TAS5717 (TAS5719) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TAS5717 TAS5719 www.ti.com SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 PIN ASSIGNMENT AND DESCRIPTIONS PIN FUNCTIONS PIN 5-V TYPE(1) TERMINATION(2) DESCRIPTION TOLERANT NAME NO. AGND 30 P Analog ground for power stage A_SEL 14 DIO This pin is monitored on the rising edge of RESET. A value of 0 makes the I2C dev address 0x54, and a value of 1 makes it 0x56. AVDD 13 P 3.3-V analog power supply AVSS 9 P Analog 3.3-V supply ground BST_A 45 P High-side bootstrap supply for half-bridge A BST_B 41 P High-side bootstrap supply for half-bridge B BST_C 40 P High-side bootstrap supply for half-bridge C BST_D 36 P High-side bootstrap supply for half-bridge D CPN 6 IO Charge-pump flying-capacitor negative connection CPP 7 IO Charge-pump flying-capacitor positive connection DVDD 27 P 3.3-V digital power supply DVSS 28 P Digital ground DVSSO 17 P Oscillator ground GND 29 P Analog ground for power stage (1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output (2) All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TAS5717 TAS5719 |
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