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RE46C190 Datasheet(PDF) 25 Page - Microchip Technology |
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RE46C190 Datasheet(HTML) 25 Page - Microchip Technology |
25 / 42 page 2010 Microchip Technology Inc. DS22271A-page 25 RE46C190 4.5 Limits Verification After all limits and LTD baseline have been entered and stored into the memory, additional test modes are available to verify if the limits are functioning as expected. Table 4-4 describes several verification tests. FIGURE 4-6: Timing Diagram for Modes T7-T10. TABLE 4-4: LIMITS VERIFICATION DESCRIPTION Limit Test Description Normal Limits Clock TEST to Mode T7 (7 clocks). With appropriate smoke level in chamber, pull FEED to VDD and hold for at least 1 ms. The HB output will indicate the detection status (High = smoke detected). Hysteresis Limits Clock TEST to Mode T8 (8 clocks). Pulse FEED and monitor HB as in Normal Limits case. Hush Limits Clock TEST to Mode T9 (9 clocks). Pulse FEED and monitor HB. Chamber Test Limits Clock TEST to Mode T10 (10 clocks). Pulse FEED and monitor HB. VDD TEST2 VSS V BST TEST VSS Min Tsetup2 = 2 µs Min PW3 = 100 µs Min T2 = 120 µs Vbst FEED VSS Min Td2 = 10 µs Min PW5 = 2 ms VDD IO VSS GLED …… … IRED …… … HB RLED |
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