A43L8316 datasheet(11/45 Pages) AMICC

Part #	A43L8316

Description	128K X 16 Bit X 2 Banks Synchronous DRAM

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Manufacturer	AMICC [AMIC Technology]

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A43L8316

Preliminary (April, 2000, Version 1.0)

10

AMIC Technology, Inc.

Mode Register Filed Table to Program Modes

Register Programmed with MRS

Address

BA

A8

A7

A6

A5

A4

A3

A2

A1

A0

Function

RFU

TM

CAS Latency

BT

Burst Length

(Note 1)

(Note 2)

Test Mode

CAS Latency

Burst Type

Burst Length

A8

A7

Type

A6

A5

A4

Latency

A3

Type

A2

A1

A0

BT=0

BT=1

0

Mode Register Set

0

Reserved

0

Sequential

0

1

Reserved

0

1

0

1

-

1

Interleave

0

1

2

Reserved

1

0

1

0

2

0

1

0

4

1

Vendor

Use

Only

0

1

3

0

1

8

Write Burst Length

1

0

Reserved

1

0

Reserved

BA

Length

1

0

1

Reserved

1

0

1

Reserved

0

Burst

1

0

Reserved

1

0

Reserved

1

Single Bit

1

Reserved

1

256(Full)

Reserved

(Note 3)

Power Up Sequence

1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200

µs.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 may be changed.

The device is now ready for normal operation.

Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.

2. If BA is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.

3. The full column burst (256bit) is available only at Sequential mode of burst type.

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