A6173081 Series

Preliminary

128K X 8 BIT HIGH SPEED CMOS SRAM

PRELIMINARY

(July, 2000, Version 0.0)

1

AMIC Technology, Inc.

Features

n Center power pinout

n Supply voltage: 5V

±10%

n Access times: 12/15 ns (max.)

n Current: Operating: -12: 170mA (max.)

-15: 165mA (max.)

Standby:

TTL: 25mA (max.)

CMOS: 8mA (max.)

n Full static operation, no clock or refreshing required

n All inputs and outputs are directly TTL compatible

n Common I/O using three-state output

n Data retention voltage: 3V (min.)

n Available in 32-pin 300mil / 400mil SOJ packages

General Description

The A6173081 is a high-speed 1,048,576-bit static

random access memory organized as 131,072 words by

8 bits and operates on a 5V power supply. It is built

using high performance CMOS process.

Inputs and three-state outputs are TTL compatible and

allow for direct interfacing with common system bus

structures.

Minimum standby power is drawn by this device when

chip enable is disable, independent of the other input

levels.

Data retention is guaranteed at a power supply voltage

as low as 3V.

Pin Configurations

n SOJ

A0

A2

A3

VCC

GND

A4

A5

A6

A8

A7

A9

A10

A11

A12

A14

A15

A16

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

VCC

OE

A1

CE

WE

A13