SN54ALS273, SN74ALS273

OCTAL D-TYPE FLIP-FLOPS

WITH CLEAR

SDAS218A – APRIL 1982 – REVISED DECEMBER 1994

Copyright

1

POST OFFICE BOX 655303

Outputs

Buffer/Storage Registers

Shift Registers

Pattern Generators

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic (N)

and Ceramic (J) 300-mil DIPs

description

These octal positive-edge-triggered flip-flops

utilize TTL circuitry to implement D-type flip-flop

logic with a direct-clear (CLR) input.

Information at the data (D) inputs meeting the

setup-time requirements is transferred to the

Q outputs on the positive-going edge of the clock

(CLK) pulse. Clock triggering occurs at a particular

voltage level and is not directly related to the

transition time of the positive-going pulse. When

CLK is at either the high or low level, the D input

signal has no effect at the output.

The SN54ALS273 is characterized for operation

over the full military temperature range of – 55

°C

to 125

°C. The SN74ALS273 is characterized for

operation from 0

°C to 70°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLR

CLK

D

OUTPUT

Q

L

X

X

L

H

↑

HH

H

↑

LL

H

H or L

X

Q0

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

CLR

1Q

1D

2D

2Q

3Q

3D

4D

4Q

GND

8Q

8D

7D

7Q

6Q

6D

5D

5Q

CLK

SN54ALS273 ...J PACKAGE

SN74ALS273 . . . DW OR N PACKAGE

(TOP VIEW)

3

2120 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

8D

7D

7Q

6Q

6D

2D

2Q

3Q

3D

4D

SN54ALS273 . . . FK PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.