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A8032 Datasheet(PDF) 4 Page - AMIC Technology |
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A8032 Datasheet(HTML) 4 Page - AMIC Technology |
4 / 12 page A8032 Series PRELIMINARY (November, 1998, Version 0.0) 3 AMIC Technology, Inc. Pin Description Pin No. Symbol I/O Description I/O Port1. Port1 is a bidirectional I/O port with internal pull-ups. Pin P1.0 and P1.1 also provide alternate functions as follows: I/O P1.0 T2 Timer/Counter2 external input/clock out 1 - 8 P1.0 - P1.7 I P1.1 T2EX Timer/Counter2 capture/reload input 9 RST I Reset input, active high. It must be kept high for at least two machine cycles to be recognized by the processor 10 - 17 P3.0 - P3.7 I/O Port3. Port3 is a bidirectional I/O port with internal pull-ups. Port3 pins also serve alternate functions as follows: I P3.0 RXD Serial receive port O P3.1 TXD Serial transmit port I P3.2 INT0 External interrupt 0 I P3.3 INT1 External interrupt 1 I P3.4 T0 Timer/Counter 0 input I P3.5 T1 Timer/Counter 1 input O P3.6 WR External data memory write strobe O P3.7 RD External data memory read strobe 18 XTAL2 O Crystal2. This is the output of crystal oscillator. It is the inversion of XTAL1 19 XTAL1 I Crystal1. This is the input of crystal oscillator. It can be driven by an external clock 20 GND I Ground 21 - 28 P2.0 - P2.7 I/O Port2. Port2 is a bidirectional I/O port with internal pull-ups. Port2 is also the multiplexed upper-order address bus during accesses to external data memory 29 PSEN O Program Store Enable, active low. The read strobe to external program memory. PSEN is activated in each machine cycle when fetching external program memory 30 ALE O Address latch enable, active high. ALE is used to enable the address latch that separates the data on Port 0 31 EA I External Access enable, active low. It is held low to enable the device to fetch code from external program memory 32 - 39 P0.7 - P0.0 I/O Port0. Port0 is an open drain, bidirectional I/O port. Port0 is also the multiplexed low-order address bus during accesses to external data memory 40 VCC I Power supply |
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