74LVT_LVTH125_6

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet

Rev. 06 — 6 March 2006

3 of 16

Philips Semiconductors

74LVT125; 74LVTH125

3.3 V quad buffer; 3-state

5.

Functional diagram

6.

Pinning information

6.1 Pinning

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram

mna228

1A

1Y

2

1

3

1OE

2A

2Y

5

4

6

2OE

3A

3Y

9

10

8

3OE

4A

4Y

12

13

11

4OE

mna229

1

EN1

1

3

2

4

6

5

10

8

9

13

11

12

mna227

nOE

nA

nY

(1) The die substrate is attached to the

exposed die pad using conductive die

attach material. It can not be used as

a supply pin or input.

Fig 4.

Pin configuration SO14, SSOP14

and TSSOP14

Fig 5.

Pin configuration DHVQFN14

125

1OE

1A

4OE

1Y

4A

2OE

4Y

2A

3OE

2Y

3A

GND

3Y

001aac476

1

2

3

4

5

6

7

8

10

9

12

11

14

13

001aac477

125

Transparent top view

2Y

3A

2A

3OE

2OE

4Y

1Y

4A

1A

4OE

6

9

5

10

4

11

3

12

2

13

terminal 1

index area