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TB5R2 Datasheet(PDF) 1 Page - Texas Instruments |
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TB5R2 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 16 page 1 FEATURES DESCRIPTION APPLICATIONS PIN ASSIGNMENTS AI AO BO CO DO AI AI BI BI C1 C1 D1 D1 D1 E2 E1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 AI AI AO E1 BO BI BI GND VCC DI DI DO E2 CO CI CI D PACKAGE (TOP VIEW) Enable Truth Table TB5R1, TB5R2 SLLS588C – NOVEMBER 2003 – REVISED JANUARY 2008 www.ti.com QUAD DIFFERENTIAL PECL RECEIVERS • Functional Replacements for the Agere BRF1A, BRF2A, BRS2A, and BRS2B These quad differential receivers accept digital data over balanced transmission lines. They translate • Pin Equivalent to General Trade 26LS32 differential input logic levels to TTL output logic • High Input Impedance Approximately 8 kΩ levels. • 4-ns Maximum Propagation Delay The TB5R1 is a pin- and function-compatible • TB5R1 Provides 50-mV Hysteresis replacement for the Agere systems BRF1A and • TB5R2 With -125-mV Threshold Offset for BRF2A; it includes 3-kV HBM and 2-kV CDM ESD Preferred State Output protection. • -1.1-V to 7.1-V Common Mode Range The TB5R2 is a pin- and function-compatible • Single 5-V 10% Supply replacement for the Agere systems BRS2A and BRS2B and incorporates a 125-mV receiver input • Slew Rate Limited (1 ns min 80% to 20%) offset, preferred state output, 3-kV HBM and 2-kV • TB5R2 Output Defaults to Logic 1 When Inputs CDM ESD protection. The TB5R2 preferred state Left Open or Shorted to VCC or GND feature places the high state when the inputs are • ESD Protection HBM > 3 kV, CDM > 2 kV open, shorted to ground, or shorted to the power supply. • Operating Temperature Range: -40C to 85C The power-down loading characteristics of the • Available in Gull-Wing SOIC (JEDEC MS-013, receiver input circuit are approximately 8 k Ω relative DW) and SOIC (D) Package to the power supplies; hence they do not load the transmission line when the circuit is powered down. • Digital Data or Clock Transmission Over The packaging for these differential line receivers Balanced Lines include a 16-pin gull wing SOIC (DW) and SOIC (D). The enable inputs of this device include internal pullup resistors of approximately 40 k Ω that are connected to VCC to ensure a logical high level input if the inputs are open circuited. FUNCTIONAL BLOCK DIAGRAM E1 E2 CONDITION 0 0 Active 1 0 Active 0 1 Disabled 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2003–2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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