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TB5R2DRE4 Datasheet(PDF) 4 Page - Texas Instruments |
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TB5R2DRE4 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 16 page www.ti.com SWITCHING CHARACTERISTICS TYPICAL CHARACTERISTICS 0 2 4 6 8 10 0 50 100 150 200 CL - Load Capacitance - pF tPLH tPHL TB5R1, TB5R2 SLLS588C – NOVEMBER 2003 – REVISED JANUARY 2008 over operating free-air temperature range unless otherwise noted parameter test conditions min typ max unit tPLH Propagation delay time, low-to-high-level output 2.5 4 CL = 0 pF (1), See Figure 2 and Figure 4 ns tPHL Propagation delay time, high-to-low-level output 2.5 4 tPLH Propagation delay time, low-to-high-level output 3 5 CL = 15 pF, See Figure 2 and Figure 4 ns tPHL Propagation delay time, high-to-low-level output 3 5 Output disable time, high-level-to-high-impedance tPHZ 4.1 12 ns output(2) CL = 5 pF, See Figure 3 and Figure 5 tPLZ Output disable time, low-level-to-high-impedance output(2) 2.8 12 ns CL = 10 pF, See Figure 2 and Figure 4 0.7 ns tskew1 Pulse width distortion, |tPHL - tPLH| CL = 150 pF, See Figure 2 and Figure 4 4 ns CL = 10 pF, TA = 75C, See Figure 2 and 0.8 1.4 ns Figure 4 Δtskew1p Part-to-part output waveform skew(3) -p CL = 10 pF, TA = -40C to 85C, See Figure 1.5 ns 2 and Figure 4 Δtskew Same part output waveform skew(3) CL = 10 pF, See Figure 2 and Figure 4 0.3 ns Output enable time, high-impedance-to-high-level tPZH 5 12 ns output(2) CL = 10 pF, See Figure 3 and Figure 4 tPZL Output enable time, high-impedance-to-low-level output(2) 4 12 ns tTLH Rise time (20%-80%) 1 3.5 ns CL = 10 pF, See Figure 2 and Figure 4 tTHL Fall time (80%-20%) 1 3.5 ns (1) The propagation delay values with a 0 pF load are based on design and simulation. (2) See Table 1. (3) Output waveform skews are when devices operate with the same supply voltage at the same temperature and have the same packages and the same test circuits. TYPICAL PROPAGATION DELAY vs LOAD CAPACITANCE A. NOTE: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed in the table above as the 0 pF load condition. The incremental increase in delay between the 0 pF load condition and the actual total load capacitance represents the extrinsic, or external delay contributed by the load. Figure 1. Typical Propagation Delay 4 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): TB5R1 TB5R2 |
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