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TMS27C256-15JE Datasheet(PDF) 3 Page - Texas Instruments

Part # TMS27C256-15JE
Description  TMS27C256 32768 BY 8-BIT UV ERASABLE TMS27PC256 32768 BY 8-BIT
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS27C256-15JE Datasheet(HTML) 3 Page - Texas Instruments

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TMS27C256 32768 BY 8BIT UV ERASABLE
TMS27PC256 32768 BY 8BIT
PROGRAMMABLE READONLY MEMORIES
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
operation
The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are
TTL level except for VPP during programming (13 V for SNAP! Pulse), and 12 V on A9 for the signature mode.
Table 2. Operation Modes
MODE†
FUNCTION
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
E
VIL
VIL
VIH
VIL
VIH
VIH
VIL
G
VIL
VIH
X
VIH
VIL
X
VIL
VPP
VCC
VCC
VCC
VPP
VPP
VPP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
A9
X
X
X
X
X
X
VH‡
VH‡
A0
X
X
X
X
X
X
VIL
VIH
CODE
DQ0 − DQ7
Data Out
Hi-Z
Hi-Z
Data In
Data Out
Hi-Z
MFG
DEVICE
DQ0 − DQ7
Data Out
Hi-Z
Hi-Z
Data In
Data Out
Hi-Z
97
04
† X can be VIL or VIH.
‡ VH = 12 V ± 0.5 V.
read / output disable
When the outputs of two or more TMS27C256s or TMS27PC256s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.
latchup immunity
Latchup immunity on the TMS27C256 and TMS27PC256 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active ICC supply current can be reduced from 30 mA to 500 µA (TTL-level inputs) or 250 µA (CMOS-level
inputs) by applying a high TTL or CMOS signal to the E pin. In this mode all outputs are in the high-impedance
state.
erasure ( TMS27C256 )
Before programming, the TMS27C256 EPROM is erased by exposing the chip through the transparent lid
to a high intensity ultraviolet light (wavelength 2537 Å). EPROM erasure before programming is necessary to
assure that all bits are in the logic high state. Logic lows are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV
intensity
× exposure time) is 15-W•s/cm2. A typical 12-mW/cm2, filterless UV lamp erases the device in 21
minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal
ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C256, the window
should be covered with an opaque label.


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