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ADSP-21363KSWZ-1AA Datasheet(PDF) 8 Page - Analog Devices |
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ADSP-21363KSWZ-1AA Datasheet(HTML) 8 Page - Analog Devices |
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8 / 56 page  Rev. G | Page 8 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 audio channels in I2S, left-justified sample pair, or right-justi- fied mode. One frame sync cycle indicates one 64-bit left/right pair, but data is sent to the FIFO as 32-bit words (that is, one- half of a frame at a time). The processor supports 24- and 32-bit I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justified formats. Precision Clock Generator (PCG) The precision clock generators (PCG) consist of two units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A and B, are identi- cal in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair. Peripheral Timers The following three general-purpose timers can generate peri- odic interrupts and be independently set to operate in one of three modes: • Pulse waveform generation mode • Pulse width count/capture mode • External event watchdog mode Each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configu- ration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables all three general-purpose timers independently. I/O PROCESSOR FEATURES The processor’s I/O provides many channels of DMA and con- trols the extensive set of peripherals described in the previous sections. DMA Controller The processor’s on-chip DMA controllers allow data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously exe- cuting its program instructions. DMA transfers can occur between the processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the parallel port (PP). See Table 4. SYSTEM DESIGN The following sections provide an introduction to system design options and power supply issues. Program Booting The internal memory of the processor boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave, or an internal boot. Booting is determined by the boot configuration (BOOT_CFG1–0) pins in Table 5. Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM. Phase-Locked Loop The processors use an on-chip phase-locked loop (PLL) to gen- erate the internal clock for the core. On power-up, the CLK_CFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1. After booting, numerous other ratios can be selected via software control. The ratios are made up of software configurable numerator val- ues from 1 to 64 and software configurable divisor values of 1, 2, 4, and 8. Power Supplies The processor has a separate power supply connection for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2 V requirement for K, B, and Y grade models, and the 1.0 V requirement for Y models. (For information on the temperature ranges offered for this product, see Operating Conditions on Page 14, Package Information on Page 15, and Ordering Guide on Page 54.) The external supply must meet the 3.3 V require- ment. All external supply pins must be connected to the same power supply. Note that the analog supply pin (AVDD) powers the processor’s internal clock generator PLL. To produce a stable clock, it is rec- ommended that PCB designs use an external filter circuit for the AVDD pin. Place the filter components as close as possible to the AVDD/AVSS pins. For an example circuit, see Figure 3. (A recommended ferrite chip is the muRata BLM18AG102SN1D.) To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (AVDD) and ground (AVSS) pins. Note that the AVDD and AVSS pins specified in Figure 3 are inputs to the processor and not the ana- log ground plane on the board—the AVSS pin should connect directly to digital ground (GND) at the chip. Table 4. DMA Channels Peripheral ADSP-2136x SPORTs 12 IDP/PDAP 8 SPI 2 MTM/DTCP 2 Parallel Port 1 Total DMA Channels 25 Table 5. Boot Mode Selection BOOT_CFG1–0 Booting Mode 00 SPI Slave Boot 01 SPI Master Boot 10 Parallel Port Boot via EPROM 11 No booting occurs. Processor executes from internal ROM after reset. |
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