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PAS6371 Datasheet(PDF) 7 Page - Pixart Imaging Inc. |
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PAS6371 Datasheet(HTML) 7 Page - Pixart Imaging Inc. |
7 / 20 page PixArt Imaging Inc. PAS6371LT CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 7 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, 2008/04/09 4. I2C TM Bus PAS6371LT supports I2C bus transfer protocol and acts as slave device. The 7-bits unique slave address is “1000000” and supports receiving / transmitting speed as maximum 400KHz. I2C Bus Overview Only two wires SDA ( serial data ) and SCL ( serial clock ) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pulled high by external pull-up resistors. Only the master can initiates a transfer ( start ), generates clock signals, and terminates a transfer ( stop ). Start and stop condition : A high to low transition of the SDA line while SCL is high defines a start condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please refer to Figure 2.1. Valid data : The data on the SDA line must be stable during the high period of the SCL clock. Within each byte, MSB is always transferred first. Read / Write control bit is the LSB of the first byte. Please refer to Figure 2.2. Both the master and slave can transmit and receive data from the bus. Acknowledge : The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. Figure 2.1 Start and Stop conditions Figure 2.2 Valid Data |
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