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TPS62263 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS62263 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 32 page V IN GND EN SW FB 1 2 3 5 4 DDCPACKAGE (TOP VIEW) DRV PACKAGE (TOPVIEW) MODE FB GND SW EN VIN 1 2 3 6 5 4 r Po w e P A D Zero-Pole Amp. Integrator Error Amplifier +1% Voltagepositioning PWM Comp. VREF Control Stage GateDriver Anti- Shoot-Through Current- LimitComparator Current- LimitComparator VREF +1% FB FB VIN GND MODE 2.25-MHz Oscillator SW1 EN V IN Softstart VOUT RAMP CONTROL Thermal Shutdown .6 Reference 0 VVREF Undervoltage Lockout 1.8 V Limit HighSide Limit LowSide Sawtooth Generator Int. Resistor Network FB RI 1 RI..N MODE Onlyin 2x2SON GND PFMComparator TPS62260, TPS62261 TPS62262, TPS62263 SLVS763D – JUNE 2007 – REVISED FEBRUARY 2011 www.ti.com PIN ASSIGNMENTS TERMINAL FUNCTIONS TERMINAL NO. I/O DESCRIPTION NO. NAME QFN TSOT23-5 2x2-6 VIN 5 1 PWR VIN power supply pin. GND 6 2 PWR GND supply pin This is the enable pin of the device. Pulling this pin to low forces the device into shutdown EN 4 3 I mode. Pulling this pin to high enables the device. This pin must be terminated. This is the switch pin and is connected to the internal MOSFET switches. Connect the SW 1 5 OUT external inductor between this terminal and the output capacitor. Feedback Pin for the internal regulation loop. Connect the external resistor divider to this pin. FB 3 4 I In case of fixed output voltage option, connect this pin directly to the output capacitor This pin is only available at QFN package option. MODE pin = high forces the device to MODE 2 I operate in fixed frequency PWM mode. MODE pin = low enables the Power Save Mode with automatic transition from PFM mode to fixed frequency PWM mode. FUNCTIONAL BLOCK DIAGRAM 4 Submit Documentation Feedback © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TPS62260 TPS62261 TPS62262 TPS62263 |
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