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AD8110-EB Datasheet(PDF) 5 Page - Analog Devices |
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AD8110-EB Datasheet(HTML) 5 Page - Analog Devices |
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5 / 29 page  REV. A AD8110/AD8111 –4– TIMING CHARACTERISTICS (Parallel) Limit Parameter Symbol Min Max Unit Data Setup Time t1 20 ns CLK Pulsewidth t2 100 ns Data Hold Time t3 20 ns CLK Pulse Separation t4 100 ns CLK to UPDATE Delay t5 0ns UPDATE Pulsewidth t6 50 ns Propagation Delay, UPDATE to Switch On or Off – 8 ns CLK, UPDATE Rise and Fall Times – 100 ns RESET Time – 200 ns t5 t6 t4 t2 t1 t3 1 0 1 0 1 = LATCHED CLK D0–D4 A0–A2 0 = TRANSPARENT UPDATE Figure 2. Timing Diagram, Parallel Mode Table II. Logic Levels VIH VIL VOH VOL IIH IIL IOH IOL RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR CLK, D0, D1, D2, CLK, D0, D1, D2, CLK, D0, D1, D2, CLK, D0, D1, D2, D3, D4, A0, A1, A2 D3, D4, A0, A1, A2 D3, D4, A0, A1, A2 D3, D4, A0, A1, A2 CE, UPDATE CE, UPDATE DATA OUT DATA OUT CE, UPDATE CE, UPDATE DATA OUT DATA OUT 2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min |
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