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MC74HCT373ADWR2G Datasheet(PDF) 1 Page - ON Semiconductor |
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MC74HCT373ADWR2G Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 9 page © Semiconductor Components Industries, LLC, 2011 June, 2011 − Rev. 12 1 Publication Order Number: MC74HCT373A/D MC74HCT373A Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs High−Performance Silicon−Gate CMOS The MC74HCT373A may be used as a level converter for interfacing TTL or NMOS outputs to High−Speed CMOS inputs. The HCT373A is identical in pinout to the LS373. The eight latches of the HCT373A are transparent D−type latches. While the Latch Enable is high the Q outputs follow the Data Inputs. When Latch Enable is taken low, data meeting the setup and hold times becomes latched. The Output Enable does not affect the state of the latch, but when Output Enable is high, all outputs are forced to the high−impedance state. Thus, data may be latched even when the outputs are not enabled. The HCT373A is identical in function to the HCT573A, which has the input pins on the opposite side of the package from the output pins. This device is similar in function to the HCT533A, which has inverting outputs. • Output Drive Capability: 15 LSTTL Loads • TTL/NMOS−Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 mA • In Compliance with the Requirements Defined by JEDEC Standard No. 7 A • Chip Complexity: 196 FETs or 49 Equivalent Gates • These Devices are Pb−Free and are RoHS Compliant Device Package Shipping† ORDERING INFORMATION MC74HCT373ANG PDIP−20 18 / Box MC74HCT373ADWG SOIC−20 38 / Rail MC74HCT373ADWR2G SOIC−20 1000 / Reel MC74HCT373AFELG SOEIAJ−20 2000 / Reel MC74HCT373ADTR2G TSSOP−20 2500 / Reel http://onsemi.com †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 20 1 1 20 MARKING DIAGRAMS SOIC−20 DW SUFFIX CASE 751D HCT373A AWLYYWWG HCT 373A ALYWG G TSSOP−20 DT SUFFIX CASE 948E SOEIAJ−20 F SUFFIX CASE 967 74HCT373A AWLYWWG 1 1 1 20 1 20 20 20 PDIP−20 N SUFFIX CASE 738 1 20 MC74HCT373AN AWLYYWWG 1 20 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) |
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