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AS1100WL Datasheet(PDF) 11 Page - ams AG |
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AS1100WL Datasheet(HTML) 11 Page - ams AG |
11 / 17 page www.austriamicrosystems.com/LED-Driver-ICs/AS1100 Revision 1.37 10 - 16 AS1100 Datasheet - D e t a i l e d D e s c r i p t i o n 8.8 Display Test Register With the display test register 0Fh all LED can be tested. In the test mode all LEDs are switched on at maximum brightness (duty cycle 31/32). All programming of digit and control registers are maintained. The format of the register is given in Table 13. Note: The AS1100 remains in display-test mode until the display-test register is reconfigured for normal operation. 8.9 No-Op Register (Cascading of AS1100) The no-operation register 00h is used when AS1100s are cascaded in order to support more than 8 digit displays. The cascading must be done in a way that all DOUT are connected to DINof the following AS1100. The LOAD and CLK signals are connected to all devices. For a write operation for example to the fifth device the command must be followed by four no-operation commands. When the LOAD signal finally goes to high all shift registers are latched. The first four devices have got no-operation commands and only the fifth device sees the intended command and updates its register. 8.10 Reset and External Clock Register This register is addressed via the serial interface. It allows to switch the device to external clock mode (If D0=1 the CLK pin of the serial interface operates as system clock input.) and to apply an external reset (D1). This brings all registers (except reg. E) to default state. For standard operation the register contents should be "00h". Table 12. Maximum Segment Current for 1-, 2-, or 3-digit Displays Number of digits Displayed Maximum Segment Current (mA) 1 10 2 20 3 30 Table 13. Display-test Register Format (address (hex) = 0xXF) Mode Register Data D7 D6 D5 D4 D3 D2 D1 D0 Normal Operation X X X X X X X 0 Display Test Mode X X X X X X X 1 Table 14. Reset and External Clock Register (address (hex) = oxXE) Mode Address Register Data code (Hex) D7 D6 D5 D4 D3 D2 D1 D0 Normal Operation, internal clock 0xXE X X X X X X 0 0 Normal Operation, external clock 0xXE X X X X X X 0 1 Reset state, internal clock 0xXE X X X X X X 1 0 Reset state, external clock 0xXE X X X X X X 1 1 |
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