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AS1312-BTDT-50 Datasheet(PDF) 7 Page - ams AG

Part # AS1312-BTDT-50
Description  Ul t ra Low Quiescent Cur rent , Hysteret ic DC-DC Step-Up Conver ter
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS1312-BTDT-50 Datasheet(HTML) 7 Page - ams AG

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AS1312
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
8.1 Hysteretic Boost Converter
Hysteretic boost converters are so called because comparators are the active elements used to determine on-off timing via current and voltage
measurements. There is no continuously operating fixed oscillator, providing an independent timing reference. As a result, a hysteretic or
comparator based converter has a very low quiescent current. In addition, because there is no fixed timing reference, the operating frequency is
determined by external component (inductor and capacitors) and also the loading on the output.
Ripple at the output is an essential operating component. A power cycle is initiated when the output regulated voltage drops below the nominal
value of VOUT (0.99 x VOUT).
Inductor current is monitored by the control loop, ensuring that operation is always dis-continuous.
The application circuit shown in Figure 1 will support many requirements. However, further optimization may be useful, and the following is
offered as a guide to changing the passive components to more closely match the end requirement.
8.1.1
Input Loop Timing
The input loop consists of the source dc supply, the input capacitor, the main inductor, and the N-channel power switch. The on timing of the N-
channel switch is determined by a peak current measurement or a maximum on time. In the AS1312, peak current is 400mA (typ) and maximum
on time is 4.2µs (typ). Peak current measurement ensures that the on time varies as the input voltage varies. This imparts line regulation to the
converter.
The fixed on-time measurement is something of a safety feature to ensure that the power switch is never permanently on. The fixed on-time is
independent of input voltage changes. As a result, no line regulation exists.
Figure 9. Simplified Boost DCDC Architecture
On time of the power switch (Faraday’s Law) is given by:
sec [volts, amps, ohms, Henry]
(EQ 1)
Applying Min and Max values and neglecting the resistive voltage drop across L1 and SW1;
(EQ 2)
(EQ 3)
SW1
SW2
CIN
COUT
L1
RLOAD
VIN
VOUT
0V
0V
Q
Q
FB
GND
IPK
T
ON
LI
PK
V
IN
I
PKRSW1
I
PKRL1
+
(
)
------------------------------------------------------------------
=
MAX
IN
MIN
PK
MIN
MIN
ON
V
I
L
T
_
_
_
=
MIN
IN
MAX
PK
MAX
MAX
ON
V
I
L
T
_
_
_
=


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