CDC7005

3.3V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER

SCAS685L− DECEMBER 2002 − REVISED JUNE 2009

7

POST OFFICE BOX 655303

Table 3. Word 2

BIT

BIT NAME

DESCRIPTION / FUNCTION

TYPE

POWER-UP

CONDITION

PIN

AFFECTED

0

C0

Register selection

W

0

1

C1

Register selection

W

1

2

HOLD

Enables the hold functionality (1 = enabled)

W

0

A4

3

NPD

PD current sources, resets the dividers and 3-states all outputs

(0 = active)

W

1

4

NRESET

RESET all dividers (0 = active)

W

1

5

ENBG

Enable bandgap (1 = enabled), see Note 2

W

1

C1

6

LOCKW 0

Lock detect window bit 0

W

0

A8

7

LOCKW 1

Lock detect window bit 1

W

0

A8

8

RES

Reserved

W

X

9

RES

Reserved

W

X

10

RES

Reserved

W

X

11

RES

Reserved

W

X

12

RES

Reserved

W

X

13

RES

Reserved

W

X

14

RES

Reserved

W

X

15

RES

Reserved

W

X

16

RES

Reserved

W

X

17

RES

Reserved

W

X

18

RES

Reserved

W

X

19

RES

Reserved

W

X

20

RES

Reserved

W

X

21

RES

Reserved

W

X

22

RES

Reserved

W

X

23

RES

Reserved

W

X

24

RES

Reserved

W

X

25

RES

Reserved

W

X

26

RES

Reserved

W

X

27

RES

Reserved

W

X

28

RES

Reserved

W

X

29

RES

Reserved

W

X

30

RES

Reserved

W

X

31

RES

Reserved

W

X

NOTE 2: The reference voltage for the charge pump and LVPECL output circuitry can be generated in two ways. One way is to enable ENBG

and the other way is to use the voltage divider circuitry (internal or external). It is recommended to enable ENBG because it gives an

accurate value and it is independent on temperature variation.