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OR2T26A-3M240 Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers |
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5 / 192 page Lucent Technologies Inc. 5 Data Sheet June 1999 ORCA Series 2 FPGAs ORCA Foundry Development System Overview The ORCA Foundry Development System interfaces to front-end design entry tools and provides the tools to produce a configured FPGA. In the design flow, the user defines the functionality of the FPGA at two points: at design entry and at the bit stream generation stage. Following design entry, the development system’s map, place, and route tools translate the netlist into a routed FPGA. Its bit stream generator is then used to generate the configuration data which is loaded into the FPGA’s internal configuration RAM. When using the bit stream generator, the user selects options that affect the func- tionality of the FPGA. Combined with the front-end tools, ORCA Foundry produces configuration data that implements the various logic and routing options dis- cussed in this data sheet. Architecture The ORCA Series FPGA is comprised of two basic elements: PLCs and PICs. Figure 1 shows an array of programmable logic cells (PLCs) surrounded by pro- grammable input/output cells (PICs). The Series 2 has PLCs arranged in an array of 20 rows and 20 columns. PICs are located on all four sides of the FPGA between the PLCs and the IC edge. The location of a PLC is indicated by its row and col- umn so that a PLC in the second row and third column is R2C3. PICs are indicated similarly, with PT (top) and PB (bottom) designating rows and PL (left) and PR (right) designating columns, followed by a number. The routing resources and configuration RAM are not shown, but the interquad routing blocks (hIQ, vIQ) present in the Series 2 series are shown. Each PIC contains the necessary I/O buffers to inter- face to bond pads. The PICs also contain the routing resources needed to connect signals from the bond pads to/from PLCs. The PICs do not contain any user- accessible logic elements, such as flip-flops. Combinatorial logic is done in look-up tables (LUTs) located in the PFU. The PFU can be used in different modes to meet different logic requirements. The LUT’s configurable medium-/large-grain architecture can be used to implement from one to four combinatorial logic functions. The flexibility of the LUT to handle wide input functions, as well as multiple smaller input functions, maximizes the gate count/PFU. The LUTs can be programmed to operate in one of three modes: combinatorial, ripple, or memory. In com- binatorial mode, the LUTs can realize any four-, five-, or six-input logic functions. In ripple mode, the high- speed carry logic is used for arithmetic functions, the new multiplier function, or the enhanced data path functions. In memory mode, the LUTs can be used as a 16 x 4 read/write or read-only memory (asynchronous mode or the new synchronous mode) or a new 16 x 2 dual-port memory. Programmable Logic Cells The programmable logic cell (PLC) consists of a pro- grammable function unit (PFU) and routing resources. All PLCs in the array are identical. The PFU, which con- tains four LUTs and four latches/FFs for logic imple- mentation, is discussed in the next section. Programmable Function Unit The PFUs are used for logic. Each PFU has 19 exter- nal inputs and six outputs and can operate in several modes. The functionality of the inputs and outputs depends on the operating mode. The PFU uses three input data buses (A[4:0], B[4:0], WD[3:0]), four control inputs (C0, CK, CE, LSR), and a carry input (CIN); the last is used for fast arithmetic functions. There is a 5-bit output bus (O[4:0]) and a carry-out (COUT). 5-2750(F).r3 Figure 2. PFU Ports PROGRAMMABLE LOGIC CELL (PLC) WD3 WD2 WD1 WD0 A4 A3 A2 A1 A0 B4 B3 B2 B1 B0 O4 O3 O2 O1 O0 PROGRAMMABLE FUNCTION UNIT CE LSR C0 CK (ROUTING RESOURCES, CONFIGURATION RAM) CIN (PFU) COUT |
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