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PCA9655EDTR2G Datasheet(PDF) 6 Page - ON Semiconductor |
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PCA9655EDTR2G Datasheet(HTML) 6 Page - ON Semiconductor |
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6 / 20 page  PCA9655E http://onsemi.com 6 Table 5. AC ELECTRICAL CHARACTERISTICS VDD = 1.65 V to 5.5 V; TA = −55°C to +125°C, unless otherwise specified. Symbol Parameter Standard Mode Fast Mode Fast Mode + Unit Min Max Min Max Min Max fSCL SCL Clock Frequency 0 0.1 0 0.4 0 1.0 MHz tBUF Bus−Free Time between a STOP and START Condition 4.7 1.3 0.5 ms tHD:STA Hold Time (Repeated) START Condition 4.0 0.6 0.26 ms tSU:STA Setup Time for a Repeated START Condition 4.7 0.6 0.26 ms tSU:STO Setup Time for STOP Condition 4.0 0.6 0.26 ms tHD:DAT Data Hold Time 0 0 0 ns tVD:ACK Data Valid Acknowledge Time (Note 8) 0.3 3.45 0.1 0.9 0.05 0.45 ms tVD:DAT Data Valid Time (Note 9) 300 50 50 450 ns tSU:DAT Data Setup Time 250 100 50 ns tLOW LOW Period of SCL 4.7 1.3 0.5 ms tHIGH HIGH Period of SCL 4.0 0.6 0.26 ms tf Fall Time of SDA and SCL (Notes 11 and 12) 300 20 + 0.1Cb (Note 10) 300 120 ns tr Rise Time of SDA and SCL 1000 20 + 0.1Cb (Note 10) 300 120 ns tSP Pulse Width of Spikes Suppressed by Input Filter (Note 13) 50 50 50 ns PORT TIMING: CL v 100 pF (See Figures 6, 9 and 10) tV(Q) Data Output Valid Time (VDD = 4.5 V to 5.5 V) (VDD = 2.3 V to 4.5 V) (VDD = 1.65 V to 2.3 V) 200 350 550 200 350 550 200 350 550 ns tSU(D) Data Input Setup Time 100 100 100 ns tH(D) Data Input Hold Time 1 1 1 ms INTERRUPT TIMING: CL v 100 pF (See Figures 9 and 10) tV(INT_N) Data Valid Time 4 4 4 ms tRST(INT_N) Reset Delay Time 4 4 4 ms 8. tVD:ACK = time for Acknowledgment signal from SCL LOW to SDA (out) LOW. 9. tVD:DAT = minimum time for SDA data out to be valid following SCL LOW. 10.Cb = total capacitance of one bus line in pF. 11. A master device must internally provide a hold time of al least 300 ns for the SDA signal (refer to VIL of the SCL signal) in order to bridge the undefined region SCL’s falling edge. 12.The maximum tffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tfis specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. 13.Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns. |
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