5/28

40

41

42

43

44

45

46

47

48

36

35

34

33

32

31

30

29

28

1

2

3

4

5

6

7

8

9

10

11

12

21

20

19

18

17

16

15

14

13

24

23

22

FB1

N.C

VREG33

N.C

VREG5A

N.C

OUTL1

DGND1

SW1

DET1

SS1

COMP1

27

26

25

37

38

39

N.C

EXTVCC

N.C

N.C

VREG5

N.C

OUTL2

DGND2

SW2

SS2

COMP2

FB2

●

Pin configuration

BD9011KV（VQFP48C）

Fig-15

●

Block functional descriptions

・

Error amp

The error amp compares output feedback voltage to the 0.8V reference voltage and provides the comparison result as COMP voltage, which is

used to determine the switching Duty. COMP voltage is limited to the SS voltage, since soft start at power up is based on SS pin voltage.

・

Oscillator (OSC)

Oscillation frequency is determined by the switching frequency pin (RT) in this block. The frequency can be set between 250kHz and 550kHz.

・

SLOPE

The SLOPE block uses the clock produced by the oscillator to generate a triangular wave, and sends the wave to the PWM comparator.

・

PWM COMP

The PWM comparator determines switching Duty by comparing the COMP voltage, output from the error amp, with the triangular wave from the

SLOPE block. Switching duty is limited to a percentage of the internal maximum duty, and thus cannot be 100% of the maximum.

・

Reference voltage (5Vreg，33Vreg)

This block generates the internal reference voltages: 5V and 3.3V.

・

External synchronization (SYNC)

Determines the switching frequency, based on the external pulse applied.

・

Over current protection (OCP)

Over current protection is activated when the VCCCL-CL voltage reaches or exceeds 90mV. When over current protection is active, Duty is low,

and output voltage also decreases. When LOFF=L, the output voltage has fallen to 70% or below and output is latched OFF. The OFF latch

mode ends when the latch is set to STB, EN.

・

Sequence control (Sequence DET)

Compares FB voltage with reference voltage (0.56V) and outputs the result as DET.

・

Protection circuits (UVLO/TSD)

The UVLO lock out function is activated when VREG falls to about 2.8V, while TSD turns outputs OFF when the chip temperature reaches or

exceeds 150℃. Output is restored when temperature falls back below the threshold value.

Pin

No.

Pin name

Function

1

OUTH2

High side FET gate drive pin 2

2

BOOT2

OUTH2 driver power pin

3

CL2

Over current detection pin 2

4

N.C

Non-connect (unused) pin

5

VCCCL2

Over current detection VCC2

6

N.C

Non-connect (unused) pin

7

VCC

Input power pin

8

VCCCL1

Over current detection CC1

9

N.C

Non-connect (unused) pin

10

CL1

Over current detection setting pin 1

11

BOOT1

OUTH1 driver power pin

12

OUTH1

High side FET gate drive pin 1

13

SW1

High side FET source pin 1

14

DGND1

Low side FET source pin 1

15

OUTL1

Low side FET gate drive pin 1

16

N.C

Non-connect (unused) pin

17

VREG5A

FET drive REG input

18

N.C

Non-connect (unused) pin

19

VREG33

Reference input REG output

20

N.C

Non-connect (unused) pin

21

FB1

Error amp input 1

22

COMP1

Error amp output 1

23

SS1

Soft start setting pin 1

24

DET1

FB detector output 1

25

STB

Standby ON/OFF pin

26

EN1

Output 1 ON/OFF pin

27

EN2

Output 2 ON/OFF pin

28

N.C

Non-connect (unused) pin

29

GND

Ground

30

GNDS

Sense ground

31

LOFF

Over current protection OFF latch

function ON/OFF pin

32

N.C

Non-connect (unused) pin

33

RT

Switching frequency setting pin

34

SYNC

External synchronous pulse input pin

35

LLM

Built-in pull-down resistor pin

36

DET2

FB detector output 2

37

SS2

Soft start setting pin 2

38

COMP2

Error amp output 2

39

FB2

Error amp input 2

40

N.C

Non-connect (unused) pin

41

EXTVCC

External power input pin

42

N.C

Non-connect (unused) pin

43

N.C

Non-connect (unused) pin

44

VREG5

FET drive REG output

45

N.C

Non-connect (unused) pin

46

OUTL2

Low side FET gate drive pin 2

47

DGND2

Low side FET source pin 2

48

SW2

High side FET source pin 2