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PPC5601PEF0MLL6R Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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PPC5601PEF0MLL6R Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
8 / 95 page MPC5602P Microcontroller Data Sheet, Rev. 4.1 Freescale Semiconductor 8 1.5.2 Crossbar switch (XBAR) The XBAR multi-port crossbar switch supports simultaneous connections between three master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus width. The crossbar allows for two concurrent transactions to occur from any master port to any slave port; but one of those transfers must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master port, arbitration logic will select the higher priority master and grant it ownership of the slave port. All other masters requesting that slave port will be stalled until the higher priority master completes its transactions. Requesting masters will be treated with equal priority and will be granted access a slave port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following features: • 3 master ports: — e200z0 core complex instruction port — e200z0 core complex Load/Store Data port —eDMA • 3 slave ports: — Flash memory (Code and Data) —SRAM — Peripheral bridge • 32-bit internal address, 32-bit internal data paths • Fixed Priority Arbitration based on Port Master • Temporary dynamic priority elevation of masters 1.5.3 Enhanced direct memory access (eDMA) The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. The hardware micro architecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. The eDMA module provides the following features: • 16 channels support independent 8-, 16- or 32-bit single value or block transfers • Supports variable-sized queues and circular queues • Source and destination address registers are independently configured to either post-increment or to remain constant • Each transfer is initiated by a peripheral, CPU, or eDMA channel request • Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block transfer • DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer and CTU • Programmable DMA channel multiplexer allows assignment of any DMA source to any available DMA channel with as many as 30 request sources • eDMA abort operation through software 1.5.4 Flash memory The MPC5602P provides 320 KB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used for instruction and/or data storage. The flash memory module is interfaced to the system bus by a dedicated flash memory controller. It supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. The module contains four 128-bit wide prefetch buffers. Prefetch buffer hits allow no-wait responses. Normal flash memory array accesses are registered and are forwarded to the system bus on the following cycle, incurring two wait-states. |
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