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AD7243BR Datasheet(PDF) 10 Page - Analog Devices |
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AD7243BR Datasheet(HTML) 10 Page - Analog Devices |
10 / 12 page AD7243 –10– REV. A AD7243–87C51 Interface A serial interface between the AD7243 and the 87C51 microcontroller is shown in Figure 14. TXD of the 87C51 drives SCLK of the AD7243, while RXD drives the serial data line of the part. The SYNC signal is derived from the port line P3.3. The 87C51 provides the LSB of its SBUF register as the first bit in the serial data stream. Therefore, the user will have to ensure that the data in the SBUF register is arranged correctly so that the don’t care bits are the first to be transmitted to the AD7243 and the last bit to be sent is the LSB of the word to be loaded to the AD7243. When data is to be transmitted to the part, P3.3 is taken low. Data on RXD is valid on the falling edge of TXD. The 87C51 transmits its serial data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. To load data to the AD7243, P3.3 is left low after the first eight bits are trans- ferred and a second byte of data is then transferred serially to the AD7243. When the second serial transfer is complete, the P3.3 line is taken high. Figure 14 shows the LDAC input of the AD7243 hard wired low. As a result, the DAC latch and the analog output will be up- dated on the sixteenth falling edge of TXD after the SYNC sig- nal for the DAC has gone low. Alternatively, the scheme used in previous interfaces, whereby the LDAC input is driven from a timer, can be used. LDAC SCLK SDIN AD7243* SYNC *ADDITIONAL PINS OMITTED FOR CLARITY P3.3 TXD RXD 87C51* Figure 14. AD7243–87C51 Interface AD7243–68HC11 Interface Figure 15 shows a serial interface between the AD7243 and the 68HC11 microcontroller. SCK of the 68HC11 drives SCLK of the AD7243 while the MOSI output drives the serial data line of the AD7243. The SYNC signal is derived from a port line (PC7 shown). For correct operation of this interface, the 68HC11 should be configured such that its CPOL bit is a 0 and its CPHA bit is a 1. When data is to be transmitted to the part, PC7 is taken low. When the 68HC11 is configured like this, data on MOSI is valid on the falling edge of SCK. The 68HC11 transmits its serial data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. To load data to the AD7243, PC7 is left low after the first eight bits are transferred and a second byte of data is then transferred serially to the AD7243. When the second serial transfer is complete, the PC7 line is taken high. Figure 15 shows the LDAC input of the AD7243 hardwired low. As a result, the DAC latch and the analog output of the DAC will be updated on the sixteenth falling edge of SCK after the respective SYNC signal has gone low. Alternatively, the scheme used in previous interfaces, whereby the LDAC input is driven from a timer, can be used. LDAC SCLK SDIN AD7243* SYNC *ADDITIONAL PINS OMITTED FOR CLARITY PC7 SCK MOSI 68HC11* Figure 15. AD7243–68HC11 Interface Multiple DAC Daisy-Chain Interface A multi-DAC serial interface is shown in Figure 16. This scheme may be used with all of the interfaces previously dis- cussed if more than one DAC is required in a system. To enable the facility the DCEN pin must be connected high on all de- vices, including the last device in the chain. SCLK AD7243* SYNC LDAC *ADDITIONAL PINS OMITTED FOR CLARITY PA1 PA2 PA3 MICROCONTROLLER PA0 SDIN DCEN SDO SCLK AD7243* SYNC LDAC SDIN DCEN SDO SCLK AD7243* SYNC LDAC SDIN DCEN SDO V DD V DD V DD Figure 16. AD7243 Daisy-Chain Configuration |
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