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LTC1068-50IG-PBF Datasheet(PDF) 10 Page - Linear Technology |
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LTC1068-50IG-PBF Datasheet(HTML) 10 Page - Linear Technology |
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10 / 30 page  LTC1068 Series 10 1068fc PIN FUNCTIONS Power Supply Pins The V+ and V– pins should each be bypassed with a 0.1µF capacitor to an adequate analog ground. The filter’s power supplies should be isolated from other digital or high voltage analog supplies. A low noise linear supply is recommended. Using a switching power supply will lower the signal-to-noise ratio of the filter. Figures 1 and 2 show typical connections for dual and single supply operation. Analog Ground Pin Thefilter’sperformancedependsonthequalityoftheanalog signal ground. For either dual or single supply operation, ananaloggroundplanesurroundingthepackageisrecom- mended. The analog ground plane should be connected to any digital ground at a single point. For single supply operation,AGNDshouldbebypassedtotheanalogground plane with at least a 0.47µF capacitor (Figure 2). Two internal resistors bias the analog ground pin. For the LTC1068, LTC1068-200 and LTC1068-25, the voltage at the analog ground pin (AGND) for single supply is 0.5 × V+ and for the LTC1068-50 it is 0.435 × V+. Clock Input Pin Any TTL or CMOS clock source with a square-wave output and50%dutycycle(±10%)isanadequateclocksourcefor the device. The power supply for the clock source should not be the filter’s power supply. The analog ground for the filter should be connected to clock’s ground at a single point only. Table 2 shows the clock’s low and high level threshold values for dual or single supply operation. Table 2. Clock Source High and Low Threshold Levels POWER SUPPLY HIGH LEVEL LOW LEVEL Dual Supply = ±5V ≥ 1.53V ≤ 0.53V Single Supply = 5V ≥ 1.53V ≤ 0.53V Single Supply = 3.3V ≥ 1.20V ≤ 0.53V A pulsed generator can be used as a clock source provided the high level ON time is at least 25% of the pulse period. Sine waves are not recommended for clock input frequen- cies less than 100kHz, since excessively slow clock rise or fall times generate internal clock jitter (maximum clock rise or fall time ≤ 1µs). The clock signal should be routed from the right side of the IC package and perpendicular to it to avoid coupling to any input or output analog signal Figure 1. Dual Supply Ground Plane Connections Figure 2. Single Supply Ground Plane Connections 0.1µF V– 1068 F01 200Ω DIGITAL GROUND V+ LTC1068 CLOCK SOURCE 0.1µF ANALOG GROUND PLANE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 STAR SYSTEM GROUND 1068 F02 200 DIGITAL GROUND FOR MODE 3, THE S NODE SHOULD BE TIED TO PIN 7 (AGND) V+ LTC1068 RA RB CLOCK SOURCE 0.1µF VAGND 0.47µF (1µF FOR STOPBAND FREQUENCIES ≤1kHz) ANALOG GROUND PLANE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 STAR SYSTEM GROUND DEVICE LTC1068 LTC1068-200 LTC1068-25 LTC1068-50 RA 10k 11.3k RB 10k 8.6k |
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