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LTC1289BCJ Datasheet(PDF) 4 Page - Linear Technology |
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LTC1289BCJ Datasheet(HTML) 4 Page - Linear Technology |
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4 / 28 page  4 LTC1289 1289fb LTC1289B LTC1289C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIH High Level Input Voltage VCC = 3.6V ● 2.1 V VIL Low Level Input Voltage VCC = 3.0V ● 0.45 V IIH High Level Input Current VIN = VCC ● 2.5 µA IIL Low Level Input Current VIN = 0V ● – 2.5 µA VOH High Level Output Voltage VCC = 3.0V V IO = 20 µA ● 2.90 IO = 400 µA 2.7 2.85 VOL Low Level Output Voltage VCC = 3.0V V IO = 20 µA ● 0.05 IO = 400 µA 0.10 0.3 IOZ High Z Output Leakage VOUT = VCC, CS High ● 3 µA VOUT = 0V, CS High ● –3 µA ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = VCC 9mA ICC Positive Supply Current CS High ● 1.5 5 mA CS High, Power Shutdown, ACLK Off ● 1.0 10 µA IREF Reference Current VREF = 2.5V ● 10 50 µA I– Negative Supply Current CS High ● 150 µA ELECTRICAL C C HARA TER STICS DIGITAL A D I DC Note 7: Two on-chip diodes are tied to each analog input which will conduct for analog voltages one diode drop below GND or one diode drop above VCC. Be careful during testing at low VCC levels, as high level analog inputs can cause this input diode to conduct, especially at elevated temperature, and cause errors for inputs near full scale. This spec allows 50mV forward bias of either diode. This means that as long as the analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. Note 8: Channel leakage current is measured after the channel selection. Note 9: To minimize errors caused by noise at the chip select input, the internal circuitry waits for two ACLK falling edges after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock an address in or data out until the minimum chip select set-up time has elasped. See Typical Peformance Characteristics curves for additional information (tsuCS vs VCC). Note 10: Increased leakage currents at elevated temperatures cause the S/H to droop, therefore it's recommended that fACLK ≥ 125kHz at 85°C and fACLK ≥ 15kHz at 25°C. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with DGND, AGND and REF –wired together (unless otherwise noted). Note 3: VCC = 3V, VREF+ = 2.5V, VREF– = 0V, V – = 0V for unipolar mode and – 3V for bipolar mode, ACLK = 2.0MHz unless otherwise specified. Note 4: These specs apply for both unipolar and bipolar modes. In bipolar mode, one LSB is equal to the bipolar input span (2VREF) divided by 4096. For example, when VREF = 2.5V, 1LSB(bipolar) = 2(2.5)/4096 = 1.22mV. V – = – 2.7V for bipolar mode. Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Recommended operating conditions. The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) |
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