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BS616LV2025DC Datasheet(PDF) 6 Page - Brilliance Semiconductor

Part # BS616LV2025DC
Description  Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable
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Manufacturer  BSI [Brilliance Semiconductor]
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Logo BSI - Brilliance Semiconductor

BS616LV2025DC Datasheet(HTML) 6 Page - Brilliance Semiconductor

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Revision 2.4
April 2002
6
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V )
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
Ω
667
THEVENIN EQUIVALENT
ALL INPUT PULSES
→
10%
90%
←
Vcc
GND
→
← 5ns
90%
10%
1.73V
OUTPUT
FIGURE 2
5.0V
OUTPUT
INCLUDING
JIG AND
SCOPE
Ω
1928
Ω
1020
5PF
FIGURE 1B
5.0V
OUTPUT
INCLUDING
JIG AND
SCOPE
Ω
1928
Ω
100PF
FIGURE 1A
1020
BSI
BS616LV2025
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
R0201-BS616LV2025
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS616LV2025-70
MIN. TYP. MAX.
BS616LV2025-55
MIN. TYP. MAX.
UNIT
t
AVAX
t
RC
Read Cycle Time
70
--
--
55
--
ns
t
AVQV
t
AA
Address Access Time
--
--
70
--
55
ns
t
E1LQV
t
ACS1
Chip Select Access Time
--
(CE1)
--
70
--
--
55
ns
t
E2LQV
t
ACS2
Chip Select Access Time
(CE2)
--
--
70
--
--
55
ns
t
BA
t
BA
Data Byte Control Access Time
(LB,UB)
--
--
35
--
--
30
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
35
--
--
30
ns
t
ELQX
t
CLZ
Chip Select to Output Low Z
(CE1,
2)
1
CE
0--
--
10--
--
ns
t
BE
t
BE
Data Byte Control to Output Low Z
(LB,U )
1
B
0
--
--
10
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
10
--
--
10
--
--
ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
(CE1,CE2)
0--
35
0
--
30
ns
t
BDO
t
BDO
Data Byte Control to Output High Z
(LB, UB)
0--
35
0
--
30
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0--
30
0
--
25
ns
t
AXOX
t
OH
Output Disable to Address Change
10
--
--
10
--
--
ns
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle .
tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
NOTE :


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