VCD

Fault condition

present

tCHGDELAY

tCD

V(CD)

I(CD)

ICHG

IDSG

Fault response

becomes active

VOUT1

V(OUT)

Note: Active High OUT version shown

bq771600, bq771601, bq771602, bq771604

SLUSAX0A – DECEMBER 2012 – REVISED SEPTEMBER 2013

www.ti.com

Figure 3 shows the behavior of the CD pin during an OV sequence.

Figure 3. CD Pin Mechanism

Sense Positive Input for Vx

This is an input to sense each single battery cell voltage. A series resistor and a capacitor across the cell for

each input is required for noise filtering and stable voltage monitoring.

Output Drive, OUT

This terminal serves as the fault signal output, and may be ordered in either active HIGH or LOW options.

Supply Input, VDD

This terminal is the unregulated input power source for the IC. A series resistor is connected to limit the current,

and a capacitor is connected to ground for noise filtering.

External Delay Capacitor, CD

This terminal is connected to an external capacitor that is used for setting the delay timer during an overvoltage

fault event.

The CD pin includes a timeout detection circuit to ensure that the output drives active even with a shorted or

open capacitor during an overvoltage event.

The capacitor connected on the CD pin rapidly charges to a voltage if any one of the cell inputs exceeds the OV

threshold. Then the delay circuit gradually discharges the capacitor on the CD pin. Once this capacitor

discharges below a set voltage, the OUT transitions from an inactive to active state.

4

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