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ADS1213P Datasheet(PDF) 5 Page - Burr-Brown (TI) |
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ADS1213P Datasheet(HTML) 5 Page - Burr-Brown (TI) |
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5 / 49 page  ADS1212, 1213 5 SBAS064A PGA +2.5V Reference +3.3V Bias Generator Clock Generator Serial Interface Second-Order ∆∑ Modulator Third-Order Digital Filter Modulator Control 14 12 13 15 16 AGND AV DD REF OUT REF IN V BIAS X IN X OUT 6 19 20 21 7 10 11 98 17 18 DSYNC CS DRDY MODE SCLK DGND DV DD SDIO SDOUT 4 5 2 3 24 1 22 23 MUX A IN1P A IN1N A IN2P A IN2N A IN3P A IN3N A IN4P A IN4N Instruction Register Command Register Data Output Register Offset Register Full-Scale Register Micro Controller ADS1213 SIMPLIFIED BLOCK DIAGRAM ADS1213P AND ADS1213U PIN DEFINITIONS TOP VIEW DIP/SOIC ADS1213P AND ADS1213U PIN CONFIGURATION PIN NO NAME DESCRIPTION 1AIN3N Inverting Input Channel 3. 2AIN2P Noninverting Input Channel 2. 3AIN2N Inverting Input Channel 2. 4AIN1P Noninverting Input Channel 1. 5AIN1N Inverting Input Channel 1. 6 AGND Analog Ground. 7VBIAS Bias Voltage Output, +3.3V nominal. 8 CS Chip Select Input. 9 DSYNC Control Input to Synchronize Serial Output Data. 10 XIN System Clock Input. 11 XOUT System Clock Output. 12 DGND Digital Ground. 13 DVDD Digital Supply, +5V nominal. 14 SCLK Clock Input/Output for serial data transfer. 15 SDIO Serial Data Input (can also function as Serial Data Output). 16 SDOUT Serial Data Output. 17 DRDY Data Ready. 18 MODE SCLK Control Input (Master = 1, Slave = 0). 19 AVDD Analog Supply, +5V nominal. 20 REFOUT Reference Output: +2.5V nominal. 21 REFIN Reference Input. 22 AIN4P Noninverting Input Channel 4. 23 AIN4N Inverting Input Channel 4. 24 AIN3P Noninverting Input Channel 3. ADS1213P ADS1213U 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 A IN3N A IN2P A IN2N A IN1P A IN1N AGND V BIAS CS DSYNC X IN X OUT DGND A IN3P A IN4N A IN4P REF IN REF OUT AV DD MODE DRDY SDOUT SDIO SCLK DV DD |
Similar Part No. - ADS1213P |
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Similar Description - ADS1213P |
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