®

ADS7804

5

BASIC OPERATION

Figure 1 shows a basic circuit to operate the ADS7804 with

a full parallel data output. Taking R/C (pin 24) LOW for a

minimum of 40ns (6

µs max) will initiate a conversion.

BUSY (pin 26) will go LOW and stay LOW until the

conversion is completed and the output registers are up-

dated. Data will be output in Binary Two’s Complement

with the MSB on pin 6. BUSY going HIGH can be used to

latch the data. All convert commands will be ignored while

BUSY is LOW.

The ADS7804 will begin tracking the input signal at the end

of the conversion. Allowing 10

µs between convert com-

mands assures accurate acquisition of a new signal.

The offset and gain are adjusted internally to allow external

trimming with a single supply. The external resistors com-

pensate for this adjustment and can be left out if the offset

and gain will be corrected in software (refer to the Calibra-

tion section).

STARTING A CONVERSION

The combination of CS (pin 25) and R/C (pin 24) LOW for

a minimum of 40ns immediately puts the sample/hold of the

ADS7804 in the hold state and starts conversion ‘n’. BUSY

(pin 26) will go LOW and stay LOW until conversion ‘n’ is

completed and the internal output register has been updated.

All new convert commands during BUSY LOW will be

ignored. CS and/or R/C must go HIGH before BUSY goes

HIGH or a new conversion will be initiated without suffi-

cient time to acquire a new signal.

The ADS7804 will begin tracking the input signal at the end

of the conversion. Allowing 10

µs between convert com-

mands assures accurate acquisition of a new signal. Refer to

Table II for a summary of CS, R/C, and BUSY states and

Figures 3 through 5 for timing diagrams.

CS and R/C are internally OR’d and level triggered. There

is not a requirement which input goes LOW first when

initiating a conversion. If, however, it is critical that CS or

R/C initiates conversion ‘n’, be sure the less critical input is

LOW at least 10ns prior to the initiating input.

To reduce the number of control pins, CS can be tied LOW

using R/C to control the read and convert modes. This will

have no effect when using the internal data clock in the serial

output mode. However, the parallel output will become

active whenever R/C goes HIGH. Refer to the Reading

Data section.

FIGURE 1. Basic Operation.

CS

R/C

BUSY

OPERATION

1

X

X

None. Databus is in Hi-Z state.

↓

0

1

Initiates conversion “n”. Databus remains

in Hi-Z state.

0

↓

1

Initiates conversion “n”. Databus enters Hi-Z

state.

01

↑

Conversion “n” completed. Valid data from

conversion “n” on the databus.

↓

1

1

Enables databus with valid data from

conversion “n”.

↓

1

0

Enables databus with valid data from

0

↑

0

Enables databus with valid data from

00

↑

New conversion initiated without acquisition

of a new signal. Data will be invalid. CS and/or

R/C must be HIGH when BUSY goes HIGH.

X

X

0

New convert commands ignored. Conversion

“n” in process.

NOTE: (1) See Figures 2 and 3 for constraints on data valid from

conversion “n-1”.

Table II. Control Line Functions for “Read” and “Convert”.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ADS7804

200

Ω

33.2k

Ω

+5V

0.1µF

10µF

+

+

2.2µF

+

+

2.2µF

Convert Pulse

40ns min

6µs max

B4

B5

B6

B7

B2

B1

B0 (LSB)

B3

B10

B9

B8

B11

B12

B13

B14

B15 (MSB)