11

®

ADS7817

D

OUT

1.4V

Test Point

3k

Ω

100pF

C

LOAD

t

r

D

OUT

V

OH

V

OL

t

f

t

dDO

t

hDO

D

OUT

DCLOCK

V

OH

V

OL

V

IL

D

OUT

Test Point

t

t

100pF

C

LOAD

3k

Ω

t

dis

CS/SHDN

90%

10%

V

IH

1

B11

2

t

en

CS/SHDN

DCLOCK

V

OL

D

OUT

V

CC

FIGURE 5. Timing Diagrams and Test Circuits for the Parameters in Table I.

NOTES: (1) Waveform 1 is for an output with internal conditions such that

the output is HIGH unless disabled by the output control. (2) Waveform 2

is for an output with internal conditions such that the output is LOW unless

disabled by the output control.

1000

100

10

1

1

10

100

1000

Sample Rate (kHz)

T

V

V

f

Allows Supply Current to Drop Directly with

Sample Rate.

Slightly with Sample Rate.

1000

100

10

1

1

10

100

1000

Sample Rate (kHz)

T

V

V

f