10

®

ADS7852

ANALOG INPUTS

The ADS7852 features eight single-ended inputs. While the

static current into each analog input is basically zero, the

dynamic current depends on the input voltage and sample

rate. Essentially, the current into the device must charge the

internal hold capacitor during the sample period. After this

capacitor has been fully charged, no further input current is

required. For optimum performance, the source driving the

analog inputs must be capable of charging the input capaci-

tance to a 12-bit settling level within the sample period. This

can be as little as 350ns in some operating modes. While the

converter is in the hold mode, or after the sampling capacitor

has been fully charged, the input impedance of the analog

input is greater than 1G

Ω.

REFERENCE

scale range of the analog input. The ADS7852 can operate

with a reference in the range of 2.0V to 2.55V corresponding

to a full-scale range of 4.0V to 5.1V.

buffer drives the capacitor DAC portion of the converter.

This is important because the buffer greatly reduces the

dynamic load placed on the reference source. Since the

glitches generated during the conversion process, it is highly

outlined in the sections that follow.

INTERNAL REFERENCE

The ADS7852 contains an onboard 2.5V reference, resulting

in a 0V to 5V input range on the analog input. The Specifi-

cations Table gives the various specifications for the internal

reference. This reference can be used to supply a small

amount of source current to an external load but the load

should be static. Due to the internal 10k

Ω resistor, a dy-

namic load will cause variations in the reference voltage,

and will dramatically affect the conversion result. Note that

even a static load will reduce the internal reference voltage

seen at the buffer input. The amount of reduction depends on

the load and the actual value of the internal “10k

Ω” resistor.

The value of this resistor can vary by

±30%.

capacitor placed as close to the ADS7852 as possible. In

addition, a 2.2

µF tantalum capacitor should be used in

parallel with the ceramic capacitor.

EXTERNAL REFERENCE

internal buffer via an on-chip 10k

Ω series resistor. Because

of this configuration, the internal reference voltage can

easily be overridden by an external reference voltage. The

voltage range for the external voltage is 2.00V to 2.55V,

corresponding to an analog input range of 4.0V to 5.1V.

While the external reference will not have to provide signifi-

series 10k

Ω resistor that is connected to the 2.5V internal

reference. Accounting for the maximum difference between

the external reference voltage and the internal reference

voltage, and the processing variations for the on-chip 10k

Ω

resistor, this current can be as high as 75

µA. In addition, the

0.1

µF ceramic capacitor placed as close to the ADS7852 as

possible. Depending on the particular reference and A/D

conversion speed, additional bypass capacitance may be

required, such as the 2.2

µF tantalum capacitor shown in the

Typical Circuit Configuration (Figure 1). Close attention

should be paid to the stability of any external reference

source that is driving the large bypass capacitors present at

BASIC OPERATION

Figure 1 shows the simple circuit required to operate the

ADS7852 with Channel 0 selected. A conversion can be

initiated by bringing the WR pin (pin 27) LOW for a

minimum of 35ns. BUSY (pin 28) will output a LOW during

the conversion process and rises only after the conversion is

complete. The 12 bits of output data will be valid on pins 15

through 26 following the rising edge of BUSY.

STARTING A CONVERSION

A conversion is initiated on the falling edge of the WR

input, with valid signals on A0, A1, A2, and CS. The

ADS7852 will enter the conversion mode on the first rising

edge of the external clock following the WR pin going

LOW. The conversion process takes 13.5 clock cycles (1.5

cycles for the DB0 decision, 2 clock cycles for the DB5

decision, and 1 clock cycle for each of the other bit deci-

sions). This allows 2.5 clock cycles for sampling. Upon

initiating a conversion, the BUSY output will go LOW

approximately 20ns after the falling edge of the WR pin.

The BUSY output will return HIGH just after the ADS7852

has finished a conversion and the output data will be valid

on pins 15 through 26. The rising edge of BUSY can be used

to latch the output data into an external device. It is recom-

mended that the data be read immediately after each conver-

sion since the switching noise of the asynchronous data

transfer can cause digital feedthrough degrading the

converter’s performance. See Figure 2.

CHANNEL ADDRESSING

The selection of the analog input channel to be converted is

controlled by address pins A0, A1, and A2. This channel

becomes active on the rising edge of WR with CS held LOW.

The data on the address pins should be stable for at least 10ns

prior to WR going HIGH.

The address pins are also used to control the power-down

functions of the ADS7852. Careful attention must be paid to

the status of the address pins following each conversion. If

the user does not want the ADS7852 to enter either of the

power-down modes following a conversion, the A0 and A1

pins must be LOW when RD and CS are returned HIGH after

reading the data at the end of a conversion (see the Power-

Down Mode section of this data sheet for more details).