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ADS7870 Datasheet(PDF) 3 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Part No. ADS7870
Description  12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM
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Maker  BURR-BROWN [Burr-Brown (TI)]
Homepage  http://www.burr-brown.com
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3
®
ADS7870
SPECIFICATIONS FOR INTERNAL FUNCTIONS(1)
(See previous section for the TOTAL DATA ACQUISITION SYSTEM)
At TA = +25°C, VDD = +5.0V, VREF = 2.5V connected to BUFIN (using internal reference), 2.5MHz CCLK and 2.5MHz SCLK, unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
ADS7870EA
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MULTIPLEXER
ON Resistance
500
OFF Resistance
1G
OFF Channel Leakage Current
VLNx = 5.2V
ON-Channel = 5.2V, OFF-Channel = 0V
100
pA
ON-Channel = 0V, OFF-Channel = 5.2V
100
pA
ON Channel Leakage Current
ON-Channel = 5.2V, OFF-Channel = 0V
100
pA
ON-Channel = 0V, OFF-Channel = 5.2V
100
pA
PGA AMPLIFIER
Input Capacitance(2)
4 to 9.7
pF
Input Impedance(2)
Common-Mode
6M
Differential
7M
Offset Voltage
100
µV
Small-Signal Bandwidth
5/Gain
MHz
Settling Time: 0.01%
G = 1
0.3
µs
G = 20
6.4
µs
ANALOG-TO-DIGITAL CONVERTER
DC CHARACTERISTICS
Resolution
12
LSB
Integral Linearity Error
0.5
LSB
Differential Linearity Error
0.5
LSB
No Missing Codes
12
Bits
Offset Error
REFIN = 2.5V
0.5
LSB
Full Scale (Gain) Error
0.02
%
Common-Mode Rejection, RTI of A/D
80
dB
Power Supply Rejection, RTI of ADS7870
External Reference, VDD = 5V ±10%
60
dB
PGA plus A/D CONVERTER
SAMPLING DYNAMICS
fCCLK = 2.5 MHz, DF = 1
Throughput Rate
48 CCLK cycles
52
kHz
Conversion Time
12 CCLK cycles
4.8
µs
Acquisition Time
28 CCLK cycles
9.6
µs
Auto Zero Time
8 CCLK cycles
3.2
µs
Aperture Delay
36 CCLK cycles
12.8
µs
Small Signal Bandwidth
5
MHz
Step Response
1 Complete Conversion Cycle
NOTES:
(1) The SPECIFICATIONS FOR THE TOTAL SYSTEM are overall analog input-to-digital output specifications. The SPECIFICATIONS FOR INTERNAL
FUNCTIONS indicate the performance of the individual functions in the ADS7870.
(2) The ADS7870 uses switched capacitor techniques for the programmable gain amplifier and A/D converter. A characteristic of such circuits is that the input
capacitance at any selected LNx pin changes during the conversion cycle.
(3) One channel “on” with its inputs grounded. All other channels “off” with sinewave voltage applied to their inputs.
(4) Ratiometric configuration exists when the input source is configured such that changes in the reference cause corresponding changes in the input voltage. The
same accuracy applies when a perfect external reference is used.
(5) The CCLK is divided by the DF value specified by the contents of register ADC CONTROL Register, bits D0 and D1 to produce DCLK. The maximum value
of DCLK is 2.5MHz.
(6) REF and BUF contribute 190
µA and 150µA (950µW and 750µW) respectively. At initial power-up the default condition for both REF and BUF functions is power
off. They can be turned on under software control by writing a “1” to D3 and D2 of the REF/OSCILLATOR CONTROL Register.
(7) For VDD < 3.0V, VREF = 2.5V not usable.




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