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DAC725JP Datasheet(PDF) 6 Page - Burr-Brown (TI) |
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DAC725JP Datasheet(HTML) 6 Page - Burr-Brown (TI) |
6 / 7 page 6 ® DAC725 The latch enable lines control which latch is being loaded. Line A 1 in combination with WR and CS enables the high byte of the DAC channel to be latched through the byte latch. The A 0 line, in conjunction with the WR and CS, latches the data for the low byte. When A2, CS, and WR are low at the same time, the data is latched through the D/A latch and the DAC changes output voltage. Each latch may be made transparent by maintaining its enable signal at logic “0”. The serial data mode is activated when both A0 and A1 are at logic low simultaneously. The data (MSB first) is clocked in to pin 13 with clock pulses on the WR pin. The data is then latched through to the DAC as a complete 16-bit word selected by A2. The CLR line resets both input latches to all zeros and sets the DAC latch to 0000 H. This is the binary code that gives a null, or zero, at the output of the DAC. The maximum clock rate of the latches is 10MHz. The minimum time between the write (WR) pulses for succes- sive enables is 20ns. In the serial input mode, the maximum rate at which data can be clocked into the input shift register is 10MHz. The timing of the control signals is given in Figure 6. OVER TEMP. INTERVAL DESCRIPTION ns, min ns, max tDW Data valid to end of WR 80 tCW CS valid to end of WR 80 tAW A0, A1, A2 valid to end of WR 80 tWP Write pulse width 80 tDH Data hold after end of WR 0 FIGURE 6. Logic Timing Diagram. FIGURE 5. Connections for Gain and Offset Adjust. t CW t AW t DW t DH t WP CS 0 A 1 , A 2 , A D0–D15, SI WR High Byte Latch Low Byte Latch D/A Latch 8 8 16 16- Bit D/A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 High Byte Latch Low Byte Latch D/A Latch 8 8 16 16- Bit D/A 270k Ω 0.0022µF Gain Adjust (A) +V CC –V CC +V CC 3.9M Ω Offset Adjust (A) * * 270k Ω 0.0022µF Gain Adjust (B) +V CC –V CC +V CC 3.9M Ω Offset Adjust (B) * * * 10k Ω to 100kΩ |
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