®

OPA655

8

DISCUSSION OF

PERFORMANCE

Amplifiers using FET input transistors operate in a similar

manner to those using bipolar transistors, with some impor-

tant advantages. In standard op amp applications, the very

low input bias currents reduce the DC error voltage due to

a high or possibly unknown source impedance. In most

OPA655 applications, the output DC error will be due only

to the low 1mV input offset voltage. Similarly, input noise

currents will contribute very little to the total output noise in

most applications. Wideband transimpedance applications

(e.g., photodiode amplifiers) will particularly benefit from

the low current noise combined with the OPA655’s very low

6nV/

√Hz input voltage noise.

The OPA655’s high gain bandwidth and very linear output

stage hold the harmonic distortion below –90dBc through

5MHz for a 2Vp-p swing into 100

Ω. Significantly less

distortion is observed at lower frequencies and/or higher

load impedance. The voltage feedback architecture supports

this level of accuracy with greater than 65dB power supply

and common mode rejection ratios. This very high dynamic

range, along with the low DC errors and noise of the FET

input stage, can provide an exceptional buffering capability

for ADC’s, PMT’s and other applications requiring high

impedance sensing of a high speed signal. For similar

distortion performance with a bipolar input stage, refer to the

OPA642.

OPERATING CONSIDERATIONS

Careful attention to PC board layout will deliver the excep-

tional performance shown in the Typical Performance Curves.

Generally, very low impedance paths to the power supplies,

along with low parasitic connections to the signal I/O pins

are required for best performance (See Layout and Intercon-

nect Considerations). Use of a guard ring around the non-

inverting input can reduce the leakage current due to com-

mon mode input signals. However, driving the guard from

the inverting node, can increase the differential input capaci-

tance, possibly leading to instability or increased broadband

noise. Non-inverting buffer applications require a very low

inductance short to be connected between the output and

inverting input to minimize peaking in the frequency re-

sponse. Use a wide trace (0.1") directly between the output

and inverting input pins on the component side of the board

for this connection.

The OPA655 is nominally designed to operate from

±5V

supplies. The maximum voltage between the supply pins

should be limited to less than 11V. Since a supply indepen-

dent bias is used, very little change in AC performance is

observed as the supply voltage is changed.

BASIC OP AMP CONNECTIONS

Figures 2 through 4 illustrate the basic op amp connections

suitable for the OPA655. The non-inverting buffer (voltage

follower) application (Figure 2) will benefit from the very

FIGURE 1. Simplified Internal Schematic.

Current

Mirror

Supply

Independent

Bias

Output

Stage

C

C

6

+In

3

2

–In

+V

S1

Output

–V

S2

+V

S2

–V

S1

4

78

5

5

Ω

5

Ω