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OPA650N Datasheet(PDF) 8 Page - Burr-Brown (TI) |
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OPA650N Datasheet(HTML) 8 Page - Burr-Brown (TI) |
8 / 12 page 8 ® OPA650 d) Connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RISO from the plot of recommended R ISO vs capacitive load. Low parasitic loads may not need an RISO since the OPA650 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required and the 6dB signal loss intrinsic to doubly terminated transmission lines is acceptable, imple- ment a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50 Ω environ- ment is not necessary on board, and in fact a higher imped- ance environment will improve distortion as shown in the distortion vs load plot. With a characteristic impedance defined based on board material and desired trace dimen- sions, a matching series resistor into the trace from the output of the amplifier is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; the total effective impedance should match the trace impedance. Multiple destination devices are best handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation loss of a doubly terminated line is unacceptable, a long trace can be series-terminated at the source end only. This will help isolate the line capacitance from the op amp output, but will not preserve signal integrity as well as a doubly terminated line. If the shunt impedance at the destination end is finite, there will be some signal attenuation due to the voltage divider formed by the series and shunt impedances. e) Socketing a high speed part like the OPA650 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable response. Best results are obtained by soldering the part onto the board. If socket- ing for the DIP package is desired, high frequency flush mount pins (e.g., McKenzie Technology #710C) can give good results. The OPA650 is nominally specified for operation using ±5V power supplies. A 10% tolerance on the supplies, or an ECL –5.2V for the negative supply, is within the maximum speci- fied total supply voltage of 11V. Higher supply voltages can break down internal junctions possibly leading to catastrophic failure. Single supply operation is possible as long as com- mon mode voltage constraints are observed. The common mode input and output voltage specifications can be inter- preted as a required headroom to the supply voltage. Observ- ing this input and output headroom requirement will allow non-standard or single supply operation. Figure 1 shows one approach to single-supply operation. 402 Ω OPA650 V AC 402 Ω R L +V S +V S V S 2 R OUT V S 2 V OUT = + 2•V AC FIGURE 1. Single Supply Operation. OFFSET VOLTAGE ADJUSTMENT If additional offset adjustment is needed, the circuit in Figure 2 can be used without degrading offset drift with temperature. Avoid external adjustment whenever possible since extraneous noise, such as power supply noise, can be inadvertently coupled into the amplifier’s inverting input terminal. Remember that additional offset errors can be created by the amplifier’s input bias currents. Whenever possible, match the impedance seen by both inputs as is shown with R3. This will reduce input bias current errors to the amplifier’s offset current. R 2 OPA650 (1)R 3 = R1 || R2 R 1 R Trim +V S –V S 20k Ω V IN or Ground Output Trim Range +V S to –V S ≅ R Trim 47k Ω R 2 R 2 R Trim 0.1µF NOTE: (1) R 3 is optional and can be used to cancel offset errors due to input bias currents. ESD PROTECTION ESD damage has been well recognized for MOSFET de- vices, but any semiconductor device is vulnerable to this potentially damaging source. This is particularly true for very high speed, fine geometry processes. ESD damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. Therefore, ESD handling precautions are strongly recommended when han- dling the OPA650. FIGURE 2. Offset Voltage Trim. |
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Similar Description - OPA650N |
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