9

OPA651

®

P

dissipated in of the output stage (P

power. Quiescent power is simply the specified no-load

supply current times the total supply voltage across the

but would, for a grounded resistive load, be at a maximum

when the output is a fixed DC voltage equal to 1/2 of either

supply voltage (assuming equal bipolar supplies). Under

back network loading. Note that it is the power dissipated

in the output stage and not in the load that determines

internal power dissipation. As an example, compute the

= 402

Ω, ±V

(4•(100

Ω||804Ω)) = 158mW. Maximum T

0.158W•150

°C/W = 109°C.

DRIVING CAPACITIVE LOADS

The OPA651’s output stage has been optimized to drive low

resistive loads. Capacitive loads, however, will decrease the

amplifier’s phase margin which may cause high frequency

peaking or oscillations. Capacitive loads greater than 10pF

should be isolated by connecting a small resistance, usually

15

Ω to 30Ω, in series with the output as shown in Figure 4.

This is particularly important when driving high capacitance

loads such as flash A/D converters. Increasing the gain from

+2 will improve the capacitive load drive due to increased

phase margin.

In general, capacitive loads should be minimized for opti-

mum high frequency performance. Coax lines can be driven

if the cable is properly terminated. The capacitance of coax

cable (29pF/foot for RG-58) will not load the amplifier

when the coaxial cable or transmission line is terminated in

its characteristic impedance.

that, from a stability standpoint, an inverting gain of –1V/V

is equivalent to a noise gain of 2.) Frequency response for

other gains are shown in the Typical Performance Curves.

The high frequency response of the OPA651 in a good

layout is very flat with frequency. However, some circuit

configurations such as those where large feedback resis-

tances are used, can produce high-frequency gain peaking.

This peaking can be minimized by connecting a small

capacitor in parallel with the feedback resistor. This capaci-

tor compensates for the closed-loop, high-frequency, trans-

fer function zero that results from the time constant formed

by the input capacitance of the amplifier (typically 2pF after

PC board mounting), and the input and feedback resistors.

The selected compensation capacitor may be a trimmer, a

fixed capacitor, or a planned PC board capacitance. The

capacitance value is strongly dependent on circuit layout and

closed-loop gain. Using small resistor values will preserve

the phase margin and avoid peaking by keeping the break

frequency of this zero sufficiently high. When high closed-

loop gains are required, a three-resistor attenuator (tee-

network) is recommended to avoid using large value resis-

tors with large time constants. The OPA651 includes an

internal 1.5pF feedback capacitor to achieve best gain of +2

PULSE SETTLING TIME

High speed amplifiers like the OPA651 are capable of

extremely fast settling time with a pulse input. Excellent

frequency response flatness and phase linearity are required

to get the best settling times. As shown in the specifications

table, settling time for a

±1V step at a gain of +2 for the

OPA651 is extremely fast. The specification is defined as

the time required, after the input transition, for the output to

settle within a specified error band around its final value. For

a 2V step, 1% settling corresponds to an error band of

±20mV, 0.1% to an error band of ±2mV, and 0.01% to an

error band of

±0.2mV. For the best settling times, particu-

larly into an ADC capacitive load, little or no peaking in the

frequency response can be allowed. Using the recommended

the settling times. Fast, extremely fine scale settling (0.01%)

requires close attention to ground return currents in the

supply decoupling capacitors. For highest performance, con-

sider the OPA642 which isolates the output stage decoupling

from the rest of the amplifier.

DIFFERENTIAL GAIN AND PHASE

Differential Gain (DG) and Differential Phase (DP) are

among the more important specifications for video applica-

tions. The percentage change in closed-loop gain over a

specified change in output voltage level is defined as DG.

DP is defined as the change in degrees of the closed-loop

phase over the same output voltage change. DG and DP are

both specified at the NTSC sub-carrier frequency of 3.58MHz.

All measurements were performed using an HP 9480.

FIGURE 4. Driving Capacitive Loads.

OPA651

C

L

R

L

R

ISO

(R

402

Ω

402

Ω

FREQUENCY RESPONSE COMPENSATION

The OPA651 is internally compensated and is stable at a

gain of 2 with a phase margin of approximately 60

°. (Note