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SN74LS375N Datasheet(PDF) 1 Page - Motorola, Inc |
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SN74LS375N Datasheet(HTML) 1 Page - Motorola, Inc |
1 / 5 page 5-528 FAST AND LS TTL DATA 4-BIT D LATCH The SN54 / 74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input /output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follow the input. When E goes LOW, the information present at the D input prior to its setup time will be retained at the Q outputs. CONNECTION DIAGRAM DIP (TOP VIEW) NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 14 13 12 11 10 9 1 2 3 4 5 6 7 16 15 8 VCC D0 D3 Q3 Q3 E2,3 Q2 Q2 D2 Q0 Q0 E0,1 Q1 Q1 D1 GND TRUTH TABLE (Each latch) NOTES: tn = bit time before enable negative-going transition. tn+1 = bit time after enable negative-going transition. tn tn+1 tn = bit time before enable negative-going transition. tn+1 = bit time after enable negative-going transition. D Q tn+1 = bit time after enable negative-going transition. H H negative-going transition. L L PIN NAMES LOADING (Note a) HIGH LOW D1 – D4 Data Inputs 0.5 U.L. 0.25 U.L. E0 – 1 Enable Input Latches 0, 1 2.0 U.L. 1.0 U.L. E2 – 3 Enable Input Latches 2, 3 2.0 U.L. 1.0 U.L. Q1 – Q4 Latch Outputs (Note b) 10 U.L. 5 (2.5) U.L. Q1 – Q4 Complimentary Latch Outputs (Note b) 10 U.L. 5 (2.5) U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 25 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. LOGIC DIAGRAM DATA ENABLE TO OTHER LATCH Q Q SN54/74LS375 4-BIT D LATCH LOW POWER SCHOTTKY ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC J SUFFIX CERAMIC CASE 620-09 N SUFFIX PLASTIC CASE 648-08 16 1 16 1 16 1 D SUFFIX SOIC CASE 751B-03 LOGIC SYMBOL VCC = PIN 16 GND = PIN 8 1 7 9 15 4 12 2 3 6 5 10 11 14 13 D0 D1 D2 D3 E0,1 E2,3 Q0 Q1 Q2 Q3 |
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