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AFL2812DYHB Datasheet(PDF) 9 Page - International Rectifier |
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AFL2812DYHB Datasheet(HTML) 9 Page - International Rectifier |
9 / 12 page www.irf.com 9 AFL28XXD Series Table 2. Nominal Resistance of Cu Wire Wire Size, AWG Resistance per ft 24 Ga 25.7 m Ω 22 Ga 16.2 m Ω 20 Ga 10.1 m Ω 18 Ga 6.4 m Ω 16 Ga 4.0 m Ω 14 Ga 2.5 m Ω 12 Ga 1.6 m Ω Incorporation of a 100µfd capacitor at the input terminals is recommended as compensation for the dynamic effects of the parasitic resistance of the input cable reacting with the complex impedance of the converter input, and to provide an energy reservoir for transient input current requirements. Figure VI. Problems of Parasitic Resistance in input Leads Vin Rtn Case Enable 1 Sync Out Sync In R p R p I Rtn I in e source System Ground e Rtn 100 µfd As an example of the effects of parasitic resistance, consider an AFL2815D operating at full power of 100W. From the specification sheet, this device has a minimum efficiency of 83% which represents an input power of more than 120W. If we consider the case where line voltage is at its’ minimum of 16V, the steady state input current necessary for this example will be slightly greater than 7.5A. If this device were connected to a voltage source with 10 feet of 20 gauge wire, the round trip (input and return) would result in 0.2 Ω of resistance and 1.5V of drop from the source to the converter. To assure 16V at the input, a source closer to 18V would be required. In applications using the paralleling option, this drop will be multiplied by the number of paralleled devices. By choosing 14 or 16 gauge wire in this example, the parasitic resistance and resulting voltage drop will be reduced to 25% or 31% of that with 20 gauge wire. Another potential problem resulting from parasitically induced voltage drop on the input lines is with regard to the operation of the enable 1 port. The minimum and maximum operating levels required to operate this port are specified with respect to the input common return line at the converter. If a logic signal is generated with respect to a ‘common’ that is distant from the converter, the effects of the voltage drop over the return line must be considered when establishing the worst case TTL switching levels. These drops will effectively impart a shift to the logic levels. In Figure VI, it can be seen that referred to system ground, the voltage on the input return pin is given by e Rtn = IRtn • RP Therefore, the logic signal level generated in the system must be capable of a TTL logic high plus sufficient additional amplitude to overcome e Rtn. When the converter is inhibited, I Rtn diminishes to near zero and eRtn will then be at system ground. |
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