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ADM8316WBX30ARJZR7 Datasheet(PDF) 11 Page - Analog Devices |
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ADM8316WBX30ARJZR7 Datasheet(HTML) 11 Page - Analog Devices |
11 / 16 page Data Sheet ADM8316/ADM8318/ADM8319/ADM8320/ADM8321/ADM8322 Rev. 0 | Page 11 of 16 APPLICATIONS INFORMATION WATCHDOG INPUT CURRENT To minimize the watchdog input current, leave WDI low for the majority of the watchdog timeout period. When driven high, WDI can draw as much as 100 µA. Pulsing WDI low to high to low at a low duty cycle reduces the effect of the large input current. When WDI is unconnected, a window comparator disconnects the watchdog timer from the reset output circuitry so that a reset is not asserted when the watchdog timer times out. NEGATIVE GOING VCC TRANSIENTS To avoid unnecessary resets caused by fast power supply transients, the ADM8316/ADM8318/ADM8319/ADM8320/ADM8321/ ADM8322 are equipped with glitch rejection circuitry. The typical performance characteristic in Figure 13 plots VCC transient duration vs. reset threshold overdrive. The curves show combinations of reset threshold overdrive and duration for which a reset is not generated for 5 V, 4.63 V, and 2.93 V reset threshold devices. For example, with the 2.93 V threshold, a transient that goes 100 mV below the threshold and lasts 80 µs typically does not cause a reset, but if the transient is any larger in reset threshold overdrive or duration, a reset generates. An optional 0.1 µF bypass capacitor mounted near VCC provides additional glitch rejection. ENSURING RESET VALID TO VCC = 0 V Both active low and active high reset outputs are guaranteed to be valid for VCC as low as 0.9 V. However, by using an external resistor with push-pull configured reset outputs, valid outputs for VCC as low as 0 V are possible. For an active low reset output, a resistor connected between RESET and ground pulls the output low when it is unable to sink current. For an active high reset output, a resistor connected between RESET and VCC pulls the output high when it is unable to source current. Use a large resistance, such as 100 kΩ, so that it does not overload the reset output when VCC is greater than 0.9 V. Figure 22. Ensuring Reset Valid to VCC = 0 V WATCHDOG SOFTWARE CONSIDERATIONS In implementing the microprocessor watchdog strobe code, quickly switching WDI low to high and then high to low (mini- mizing WDI high time) is desirable for current consumption reasons. However, a more effective way of using the watchdog function can be considered. A low to high to low WDI pulse within a given subroutine prevents the watchdog from timing out. However, if the sub- routine becomes stuck in an infinite loop, the watchdog cannot detect this because the subroutine continues to toggle WDI. A more effective coding scheme for detecting this error involves using a slightly longer watchdog timeout. In the program that calls the subroutine, WDI is set high. The subroutine sets WDI low when it is called. If the program executes without error, WDI is toggled high and low with every loop of the program. If the subroutine enters an infinite loop, WDI is kept low, the watchdog times out, and the microprocessor is reset (see Figure 23). Figure 23. Watchdog Flow Diagram Figure 24. Typical Application Circuit ADM8316/ ADM8318/ ADM8319 VCC RESET 100k Ω ADM8318/ ADM8319/ ADM8321/ ADM8322 VCC RESET 100 kΩ START SET WDI HIGH PROGRAM CODE SUBROUTINE SET WDI LOW RETURN INFINITE LOOP: WATCHDOG TIMES OUT RESET RESET RESET WDI I/O MR ADM8316 VCC MICROPROCESSOR |
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