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A3PN060-ZVQG100 Datasheet(PDF) 27 Page - Microsemi Corporation |
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A3PN060-ZVQG100 Datasheet(HTML) 27 Page - Microsemi Corporation |
27 / 114 page ProASIC3 nano Flash FPGAs Revision 11 2-13 Figure 2-3 • Input Buffer Timing Model and Delays (example) tPY (R) PAD Y Vtrip GND tPY (F) Vtrip 50% 50% VIH VCC VIL tDIN (R) DIN GND tDIN (F) 50% 50% VCC PAD Y tPY D CLK Q I/O Interface DIN tDIN To Array tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) |
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