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A3PN060-ZVQG100 Datasheet(PDF) 39 Page - Microsemi Corporation |
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A3PN060-ZVQG100 Datasheet(HTML) 39 Page - Microsemi Corporation |
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39 / 114 page  ProASIC3 nano Flash FPGAs Revision 11 2-25 3.3 V LVCMOS Wide Range Table 2-33 • Minimum and Maximum DC Input and Output Levels for 3.3 V LVCMOS Wide Range 3.3 V LVCMOS Wide Range Equivalent Software Default Drive Strength Option3 VIL VIH VOL VOH IOL IOH IIL1 IIH2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. VmA mA µA4 µA4 100 µA 2 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10 100 µA 4 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10 100 µA 6 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10 100 µA 8mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 4. Currents are measured at 85°C junction temperature. 5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JESD8-B specification. 6. Software default selection highlighted in gray. |
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