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A3977SLPTR-T Datasheet(PDF) 5 Page - Allegro MicroSystems |
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A3977SLPTR-T Datasheet(HTML) 5 Page - Allegro MicroSystems |
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5 / 19 page  Microstepping DMOS Driver with Translator A3977 5 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted) Characteristic Symbol Test Conditions Min. Typ. Max. Units Output Drivers Load Supply Voltage Range VBB Operating 8.0 – 35 V During sleep mode 0 – 35 V Output Leakage Current IDSS VOUT = VBB – <1.0 20 μA VOUT = 0 V – <1.0 -20 μA Output On Resistance rDS(on) Source driver, IOUT = -2.5 A – 0.45 0.57 Ω Sink driver, IOUT = 2.5 A – 0.36 0.43 Ω Body Diode Forward Voltage VF Source diode, IF = -2.5 A – – 1.4 V Sink diode, IF = 2.5 A – – 1.4 V Motor Supply Current IBB fPWM < 50 kHz – – 8.0 mA Operating, outputs disabled – – 6.0 mA Sleep mode – – 20 μA Control Logic Logic Supply Voltage Range VDD Operating 3.0 5.0 5.5 V Logic Input Voltage VIN(1) 0.7VDD –– V VIN(0) – – 0.3VDD V Logic Input Current IIN(1) VIN = 0.7VDD -20 <1.0 20 μA IIN(0) VIN = 0.3VDD -20 <1.0 20 μA Maximum STEP Frequency fSTEP 500* – – kHz HOME Output Voltage VOH IOH = -200 μA 0.7VDD – – V VOL IOL = 200 μA – – 0.3VDD V Blank Time tBLANK Rt = 56 kΩ, Ct = 680 pF 700 950 1200 ns Fixed Off Time toff Rt = 56 kΩ, Ct = 680 pF 30 38 46 μs Mixed Decay Trip Point PFDH – 0.6VDD –V PFDL – 0.21VDD –V Ref. Input Voltage Range VREF Operating 0 – VDD V Reference Input Current IREF – 0 ±3.0 μA Gain (Gm) Error (note 3) EG VREF = 2 V, Phase Current = 38.27% – – ±10 % VREF = 2 V, Phase Current = 70.71% – – ±5.0 % VREF = 2 V, Phase Current = 100.00% – – ±5.0 % Crossover Dead Time tDT SR enabled 100 475 800 ns Continued on the next page… |
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