IRMCF143S

4

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List of Figures

Figure 1. Typical Application Block Diagram Using IRMCF143S.............................................................................. 5

Figure 2. Pinout of IRMCF143S ................................................................................................................................ 6

Figure 3. IRMCF143S Block Diagram ....................................................................................................................... 7

Figure 4. IRMCF143S Application Diagram .............................................................................................................. 8

Figure 5. Crystal circuit example ............................................................................................................................. 16

Figure 6. Voltage droop and S/H hold time ............................................................................................................. 17

Figure 7. Op amp output capacitor .......................................................................................................................... 18

Figure 8. SYNC timing ............................................................................................................................................. 19

Figure 9. Gatekill timing ........................................................................................................................................... 20

Figure 10. ITRIP timing............................................................................................................................................ 20

Figure 11. Interrupt timing ....................................................................................................................................... 21

Figure 12. I

2C Timing............................................................................................................................................... 22

Figure 13. SPI write timing ...................................................................................................................................... 23

Figure 14. SPI read timing ....................................................................................................................................... 24

Figure 15. UART timing ........................................................................................................................................... 25

Figure 16. CAPTURE timing.................................................................................................................................... 26

Figure 17. JTAG timing............................................................................................................................................ 27

Figure 18. PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH/BRAKE output .............................................. 28

Figure 19. All digital I/O except PWM output........................................................................................................... 28

Figure 20. RESET, GATEKILL I/O .......................................................................................................................... 28

Figure 21. Analog input ........................................................................................................................................... 29

Figure 22. Analog operational amplifier output and AREF I/O structure ................................................................. 29

Figure 23. VSS,AVSS pin I/O structure ................................................................................................................... 29

Figure 24. VDD1,VDDCAP pin I/O structure ........................................................................................................... 30

Figure 25. XTAL0/XTAL1 pins structure.................................................................................................................. 30